Gate Stack Integration for Threshold Voltage Control
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Solution Overview
Problem
Conventional poly-silicon gates in semiconductor devices face performance issues due to boron penetration and depletion effects as semiconductor devices scale down, necessitating the use of work function metals for high-k gate dielectric layers, but integrating transistors with different conductivity types and threshold voltages poses challenges in manufacturing.
Innovation Solution
A manufacturing method that involves treating the gate dielectric layer and/or bottom barrier layer locally to modify threshold voltages and adjusting the thickness of work function layers, allowing for the efficient integration of gate stacks with different conductivity types and threshold voltages by forming distinct components in specific regions of the semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional poly-silicon gates are used in semiconductor devices, then manufacturing process is simple, but performance deteriorates due to boron penetration and depletion effects as devices scale down
Solution Approach 1:
The patent changes the material parameters of the gate electrode from conventional poly-silicon to work function metals (such as titanium nitride, tantalum nitride, or tungsten) with specific work function values. This parameter change eliminates boron penetration and depletion effects while maintaining manufacturability through established PVD or CVD deposition processes.
Solution Approach 2:
The patent employs composite gate stack structures combining high-k gate dielectric layers (such as hafnium oxide, silicon oxide, or silicon nitride) with work function metal layers. This composite structure achieves both improved device performance and controlled threshold voltages while remaining compatible with existing manufacturing processes.
2Reliability
If work function metals are used to replace poly-silicon gates, then device performance improves, but integrating transistors with different conductivity types and threshold voltages becomes more complex
Solution Approach 1:
The patent segments the gate electrode into multiple work function metal layers with different conductivity types (n-type and p-type) and different work function values. This segmentation allows different regions of the gate to provide different threshold voltages for nMOS and pMOS transistors, enabling efficient integration of complementary metal-oxide-semiconductor devices with improved performance.
3Adaptability or versatility
If gate stacks are designed with different structures for different conductivity types, then different threshold voltages are achieved, but manufacturing efficiency decreases
Solution Approach 1:
The patent designs a universal gate stack structure using work function metals that can serve multiple functions: providing both n-type and p-type conductivity, achieving different threshold voltages, and maintaining compatibility with standard semiconductor manufacturing processes. This multi-functionality allows a single gate stack design to support both nMOS and pMOS transistors, significantly improving manufacturing efficiency while maintaining threshold voltage differentiation.
Data Source
AI summary
A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.