Semiconductor Gate Stack Void Filling for FinFET Metal Gates
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Solution Overview
Problem
Existing FinFET fabrication processes face challenges in forming a three-dimensional strained channel, particularly due to void formation in sacrificial layers caused by high fin aspect ratios and narrow fin pitches, which hinder the formation of metal gates.
Innovation Solution
A method involving the formation of sacrificial gate stacks over fin features, followed by patterning and removal of voids with sacrificial fill layers, and subsequent formation of sidewall spacers to pattern metal gates, ensuring uniform deposition and removal of sacrificial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fin aspect ratio is increased to achieve higher device density, then productivity is improved, but void formation in sacrificial layers occurs due to narrow fin pitches
Solution Approach 1:
A sacrificial fill layer is introduced as an intermediary material to fill voids in the sacrificial gate stack. This mediator material enables uniform metal gate deposition by eliminating voids that would otherwise cause defects, while allowing the fin structure to maintain its high aspect ratio for improved device density
Solution Approach 2:
The sacrificial fill layer is deposited beforehand to fill voids in the sacrificial gate stack before metal gate formation. This preliminary action prevents void-related defects during subsequent metal gate deposition, ensuring reliable device fabrication while maintaining high fin aspect ratios for improved productivity
2Manufacturing precision
If sacrificial gate stacks are used to enable metal gate formation, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The sacrificial gate stack serves as a temporary structure that is deposited, used to define the metal gate pattern, and then removed. This approach enables precise metal gate formation while the additional steps are confined to specific process stages, managing overall process complexity through structured temporary structure usage
3Area of stationary object
If fin pitch is reduced to increase functional density, then area is reduced, but void formation in sacrificial layers is exacerbated
Solution Approach 1:
The sacrificial fill layer acts as a mediator that fills voids created by narrow fin pitches. This enables the fabrication of high-density devices with reduced chip area while preventing void-related defects that would compromise device reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the formation of metal gates by eliminating voids, improving yield and ensuring smooth transition to metal gate structures, thereby addressing the challenges of void formation in FinFET fabrication.
Implementation Method 1
depositing a dielectric layer on the sidewall of the first gate stack
Implementation Method 2
depositing a dielectric layer on the sidewall of the first gate stack
Data Source
AI summary
A method includes: receiving a substrate; depositing a first gate layer over the substrate; patterning the first gate layer to form a first gate stack and leaving at least one void exposed from a sidewall of the first gate stack; depositing a dielectric layer on the sidewall of the first gate stack; and removing a first portion of the dielectric layer from the sidewall of the first gate stack while leaving a second portion of the dielectric layer to fill the at least one void.