Gate-Stacked Memory Channels With Uniform Crystal Orientation
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and achieving high-performance memory cells due to variations in channel layer crystal orientations, leading to inconsistent cell properties and reduced productivity.
Innovation Solution
A semiconductor device with a gate stacking structure and channel structures where multiple channel layers have the same crystal orientation, achieved through a manufacturing process involving sacrificial insulating layers, heat treatment, and metal-induced crystallization, resulting in improved crystallization and reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing processes are used to form channel layers, then the manufacturing process is simple, but the channel layers have variations in crystal orientation leading to inconsistent cell properties
Solution Approach 1:
A metal layer is formed on the substrate before forming the channel layers. This metal layer serves as a crystallization catalyst that induces single-crystal or quasi-single-crystal structures in the channel layers during subsequent heat treatment, ensuring uniform crystal orientation before the channel layers are fully formed
Solution Approach 2:
The manufacturing process utilizes controlled heat treatment parameters (temperature, time, atmosphere) to transform the channel layers from amorphous or polycrystalline states to single-crystal or quasi-single-crystal states with uniform orientation, leveraging the catalytic effect of the metal layer to achieve consistent crystallographic properties
2Reliability
If channel layers with different crystal orientations are used, then various semiconductor materials can be employed, but cell current and performance become inconsistent
Solution Approach 1:
The metal layer is selectively positioned at the interface with the channel layers to provide localized crystallization catalysis. This localized intervention ensures that only the channel layers in contact with the metal layer receive the crystallization effect, while maintaining the ability to use different semiconductor materials with appropriate crystal structures
Solution Approach 2:
The metal layer creates homogeneous crystallization conditions across all channel layers, inducing uniform single-crystal or quasi-single-crystal structures with consistent orientation. This homogenizes the electrical properties and cell current characteristics regardless of the specific semiconductor material used
3Productivity
If amorphous channel layers are formed, then the manufacturing process is straightforward, but the cell current is lower and performance is reduced
Solution Approach 1:
The process utilizes phase transition from amorphous to crystalline state through controlled heat treatment. The metal layer catalyzes this phase transition, transforming the channel layers from low-current amorphous states to high-current single-crystal or quasi-single-crystal states without requiring complete process redesign
Solution Approach 2:
The mechanical or chemical process of directly forming crystalline channel layers is replaced by a thermal process assisted by metal-induced crystallization. This substitution achieves superior crystal quality through thermal energy activation rather than complex mechanical or chemical synthesis methods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enhances cell current and uniformity, leading to increased performance and productivity of semiconductor devices by stabilizing channel layers with the same crystal orientation, thereby improving memory cell properties.
Implementation Method 1
The plurality of channel layers have a single crystal structure or a quasi-single crystal structure that have a same crystal orientation and are formed by performing a heat treatment process that crystallizes the plurality of preliminary channel layers
Implementation Method 2
forming a plurality of channel layers, and forming a plurality of gate electrodes. The stacking structure includes a plurality of sacrificial insulating layers and a plurality of insulating layers alternately stacked with each other
Data Source
AI summary
A semiconductor device includes a gate stacking structure that includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked with each other, and a plurality of channel structures that penetrate the gate stacking structure. The plurality of channel structures include a first channel structure that includes a first channel layer, and a plurality of second channel structures adjacent to the first channel structure and that include a plurality of second channel layers. The first channel layer in the first channel structure and the plurality of second channel layers in the plurality of second channel structures have a same crystal orientation.