3D Gate Stair Contact Structure for Dense Memory Isolation
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Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited, and there is a need for a more reliable and densely integrated semiconductor memory solution that surpasses the limitations of two-dimensional devices.
Innovation Solution
A semiconductor device with a gate structure comprising interleaved conductive and insulating layers forming a stair structure, contact plugs extending through these layers, and insulating spacers to enhance electrical connectivity and isolation, along with a manufacturing method that involves forming a stack of material layers, creating a stair structure, and oxidizing surfaces to form spacers and contact plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional semiconductor device structure is used, then manufacturing process is simple, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by forming a stack of alternating insulating and conductive layers that extend in the vertical direction. This dimensional change allows multiple memory cells to be stacked above a single footprint area, dramatically increasing integration density while maintaining manufacturing feasibility through sequential layer deposition and patterning processes
2Ease of manufacture
If insulating spacers with thickness equal to insulating layers are used, then manufacturing is simplified, but electrical isolation effectiveness is reduced
Solution Approach 1:
The patent applies local quality by making the insulating spacer thickness different from the insulating layer thickness. Specifically, the insulating spacer is formed with a greater thickness than the insulating layers to provide enhanced electrical isolation. This localized variation in thickness is applied only where needed for isolation, while other dimensions maintain the original layer specifications, balancing manufacturing simplicity with isolation effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases integration density and reliability by allowing for superior electrical connectivity and isolation, enabling more efficient use of space and improving the performance of semiconductor memory devices.
Implementation Method 1
forming an insulating spacers by oxidizing a surface of the second material layers exposed through the first opening
Data Source
AI summary
A semiconductor device may include a gate structure including conductive layers and insulating layers that are alternately stacked and including a stair structure for exposing at least one of the conductive layers, a contact plug that extends through the gate structure and that is electrically connected to a uppermost conductive layer that is exposed by the stair structure, and insulating spacers that are disposed between remaining conductive layers, among the conductive layers, and the contact plug. The insulating layers may each have a first thickness, and the insulating spacers may each have a second thickness smaller than the first thickness.