Power Transistor Gate Stress Test Circuit With Decoupled Contact Pads
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Solution Overview
Problem
Existing power electronic circuits face challenges in stress testing power transistors without damaging control circuits, require dedicated protection components, and cannot test high-side and low-side transistors simultaneously due to shared contact pads.
Innovation Solution
A power electronic circuit design where contact pads are decoupled during stress testing to apply different electrical potentials, allowing simultaneous testing of high-side and low-side transistors without subjecting control circuits to high stress voltages, and encapsulation connects pads for integrated operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress voltage is applied to test power transistor gates, then transistor defects can be identified, but control circuits may be damaged by high stress voltages
Solution Approach 1:
The contact pads are segmented into two separate pads: a first contact pad for the power transistor source and a second contact pad for the control circuit. This segmentation allows independent voltage application - stress voltage can be applied to the first pad while the control circuit connected to the second pad remains at safe voltage levels, thus protecting the control circuit from damage while enabling transistor testing
Solution Approach 2:
The decoupling of contact pads acts as an intermediary mechanism that separates the stress voltage path from the control circuit path. By physically separating the connection points, the control circuit is shielded from direct exposure to harmful stress voltages while the power transistor can still be tested through the isolated first contact pad
2Object-affected harmful factors
If dedicated protection components are added to protect control circuits, then control circuits are protected from stress voltages, but device complexity increases
Solution Approach 1:
The protection function is extracted from the circuit by physically separating the contact pads rather than adding protection components within the circuit. The first contact pad is taken out as a separate testing interface for the power transistor, while the second contact pad serves as the protected interface for the control circuit, eliminating the need for additional protection components
Solution Approach 2:
The second contact pad serves multiple functions: it provides a safe connection point for the control circuit during normal operation and during stress testing. This multi-functional design protects the control circuit without requiring separate protection components, thereby reducing overall device complexity
3Device complexity
If high-side and low-side transistors share contact pads, then circuit integration is improved, but simultaneous stress testing of both transistors becomes impossible
Solution Approach 1:
The contact pads are segmented into first and second pads, enabling independent testing of high-side and low-side transistors. Each transistor can be connected to the first contact pad for stress testing while maintaining proper circuit integration through the second contact pad, thus achieving both integration and simultaneous testing capability
Solution Approach 2:
The testing capability is extended to another dimension by creating separate contact interfaces. Instead of sharing a single contact pad, the circuit provides separate first and second contact pads that enable parallel testing paths, effectively increasing testing throughput while maintaining circuit integration
Data Source
AI summary
Provided is a power electronic circuit comprising at least one power transistor the gate of which is coupled to a control circuit, and the source of which is coupled to a first contact pad, wherein the control circuit is coupled to a second contact pad, and wherein the first and second contact pads are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate of the power transistor, and configured to be coupled to each other when the power transistor and control circuit are encapsulated.