Gate-Strip Poly Extension Layout for PMOS-NMOS Threshold Balance
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, particularly in managing the poly extension effect, which affects the threshold voltage of transistors and overall circuit performance, as existing methods struggle to optimize the positioning of poly cut patterns to balance the poly extension effects of PMOS and NMOS transistors.
Innovation Solution
A method is developed to generate layout designs by determining the difference in poly extension effects between PMOS and NMOS transistors, adjusting the positioning of poly cut patterns to optimize transistor performance, involving the generation of active zone patterns, gate-strip patterns, and determining the appropriate intersection points to create segments that enhance circuit performance based on the poly extension effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If poly cut patterns are positioned to reduce poly extension effect in one transistor type, then threshold voltage control improves for that transistor type, but the poly extension effect becomes unbalanced between PMOS and NMOS transistors
Solution Approach 1:
The patent applies different poly extension lengths to different transistor types (PMOS and NMOS) within the same cell structure. Specifically, the gate strip extends a first length over the PMOS transistor channel and a second length over the NMOS transistor channel, where the first and second lengths are different. This local differentiation allows each transistor type to have optimized threshold voltage characteristics while maintaining overall cell functionality.
Solution Approach 2:
The gate strip is segmented into different extension lengths corresponding to different transistor types. The poly cut patterns are strategically positioned to create distinct gate extension segments, where one segment extends further over PMOS transistors and another segment extends further over NMOS transistors. This segmentation enables independent optimization of poly extension effects for each transistor type.
2Ease of manufacture
If the gate strip extends uniformly over all transistors, then layout simplicity is maintained, but the poly extension effects cannot be optimized for different transistor types
Solution Approach 1:
Instead of uniform gate extension, the patent implements local quality variations by extending the gate strip different lengths over PMOS and NMOS transistors. The gate strip maintains continuous structure for manufacturing simplicity while introducing localized extension length differences to optimize each transistor type's performance characteristics.
Solution Approach 2:
The patent changes the geometric parameter of gate strip extension length based on transistor type. By varying the extension length parameter (first length for PMOS, second length for NMOS), the design achieves optimized poly extension effects for each transistor type while maintaining a relatively simple continuous gate strip structure.
3Manufacturing precision
If poly cut patterns are added to optimize poly extension effects, then transistor threshold voltage control improves, but device complexity increases
Solution Approach 1:
The patent uses poly cut patterns to segment the gate strip into different extension length sections. These cuts create distinct segments that extend different lengths over PMOS and NMOS transistors, enabling precise threshold voltage control through controlled segmentation rather than complex multi-layer structures.
Solution Approach 2:
The patent optimizes threshold voltage control by changing the extension length parameter of the gate strip segments. Rather than adding complex structures, the solution modifies the geometric parameter (extension length) of existing gate strip segments to achieve the desired electrical characteristics.
Data Source
AI summary
A method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. Creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. Creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.