Gate Structure for Non-Volatile Memory Back Tunneling
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Solution Overview
Problem
Charge-trap NAND flash memory devices face issues with erase saturation due to back tunneling, which affects their performance and reliability.
Innovation Solution
A gate structure is designed with a tunnel oxide layer, a charge trap layer, and a blocking dielectric layer, where the blocking dielectric layer has a high dielectric constant material, and spacers with specific dielectric constants are used to prevent back tunneling by uniformly generating an electric field and reducing concentration on the edge regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used in charge-trap NAND flash memory, then the device can be scaled down easily, but erase saturation occurs due to back tunneling which degrades performance and reliability
Solution Approach 1:
The patent applies local quality by creating spacers with specific dielectric constants positioned at edge regions of the gate structure. These spacers have different dielectric properties than the bulk gate structure, specifically designed to reduce electric field concentration at critical edge regions where back tunneling occurs, thereby locally addressing the harmful effect without changing the overall scaled-down structure
Solution Approach 2:
The patent changes the dielectric constant parameter of materials used in spacers to control electric field distribution. By selecting materials with specific dielectric constants for different spacer regions, the patent modifies the electrical parameters of the gate structure to prevent charge accumulation and reduce back tunneling, thus improving erase operation characteristics
2Reliability
If the gate structure uses high dielectric constant materials in blocking dielectric layer and spacers, then back tunneling is prevented, but the device structure and manufacturing process become more complex
Solution Approach 1:
The patent segments the gate structure into multiple functional layers including tunnel oxide layer, charge trap layer, blocking dielectric layer, and multiple spacers with different dielectric constants. This segmentation allows each layer to perform its specific function optimally while managing complexity through modular design, where each segment addresses a particular aspect of preventing back tunneling
Solution Approach 2:
The patent employs composite materials by combining multiple dielectric layers with different properties (tunnel oxide, charge trap layer, blocking dielectric layer) and spacers with varying dielectric constants. This composite structure leverages the strengths of each material to achieve reliable prevention of back tunneling while maintaining scalability of the overall device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed gate structure effectively prevents erase saturation caused by back tunneling, enhancing the erasing operation characteristics and reliability of the non-volatile memory device.
Implementation Method 1
A blocking dielectric layer pattern is formed on the charge trap layer pattern and includes at least one dielectric layer. The uppermost dielectric layer of the blocking dielectric layer pattern includes a material having a dielectric constant greater than that of a material included in the tunnel oxide layer pattern.
Implementation Method 2
data is recorded by storing charges in a charge trap layer pattern serving as an insulator or erasing charges from the charge trap layer pattern
Data Source
AI summary
A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.