Semiconductor Gate Structure With Trimmed Dielectric Sidewalls
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits increases processing complexity and manufacturing challenges, particularly in preventing current leakage due to the merging of sidewalls and residual fluorine (F) in dielectric layers during etching processes.
Innovation Solution
A method involving etching and post-treatment processes to form dielectric layers between semiconductor materials, including NF3 plasma etching to trim overhangs and NH3 plasma treatment to remove F residuals, ensuring the dielectric layer's integrity and preventing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity and manufacturing challenges increase
Solution Approach 1:
The patent applies preliminary action by performing a depositing step before the etching step to form a protective dielectric layer on the sidewalls. This pre-formed layer prevents merging of sidewalls during subsequent etching processes, addressing the complexity issue before it arises while enabling continued scaling for improved productivity
2Manufacturing precision
If etching process is used to trim overhang of dielectric layer, then sidewall merging is prevented, but residual fluorine is left behind causing current leakage
Solution Approach 1:
The patent converts the harmful residual fluorine left by NF3 plasma etching into a beneficial outcome by introducing an NH3 plasma treatment step. The NH3 plasma reacts with and removes the fluorine residues, transforming the harmful byproduct into a clean interface that prevents current leakage while maintaining the precision benefits of the etching process
Solution Approach 2:
The patent introduces NH3 plasma as an intermediary substance between the NF3 etching process and the final device structure. This intermediary step mediates the harmful effect of fluorine residues by chemically reacting with and removing them, allowing the system to achieve both precise sidewall alignment and reliable current leakage prevention
3Reliability
If dielectric layer thickness is maintained to prevent current leakage, then reliability is improved, but sidewall merging occurs due to overhang
Solution Approach 1:
The patent applies segmentation by dividing the dielectric layer formation into distinct functional portions: a protective sidewall portion formed on the sidewalls and a bottom portion formed at the base. This segmentation allows the sidewall portion to be trimmed back via etching to prevent merging, while the bottom portion maintains sufficient thickness for current leakage prevention, resolving the contradiction between the two requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the risk of current leakage by maintaining the dielectric layer's thickness and purity, enhancing the semiconductor device's performance and reliability.
Implementation Method 1
performing an etching process to trim off at least a portion of the overhang of the sidewall portion of the dielectric layer
Implementation Method 2
performing a post-treatment process to remove F residuals left behind by the etching process
Data Source
AI summary
A method of forming a semiconductor device structure includes forming a sacrificial gate stack over a portion of a fin structure, removing an exposed portion of the fin structure to expose a portion of a substrate and a surface of a semiconductor layer of the fin structure, depositing a first semiconductor material on the exposed portion of the substrate, depositing a dielectric layer, performing an etching process to trim off at least a portion of an overhang of a sidewall portion of the dielectric layer, removing the sidewall portion of the dielectric layer, and forming a second semiconductor material on a bottom portion of the dielectric layer.