Semiconductor Gate Structure With Anti-Reaction Layer for Lower Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in improving gate electrode performance for nano-FETs, particularly in reducing gate resistance and achieving a threshold voltage boost, which are essential for enhancing device integration density and efficiency.
Innovation Solution
A method involving the formation of gate electrodes with an anti-reaction layer and a metal cap layer, where the anti-reaction layer is used to impede the selective deposition of the metal cap layer, allowing for a p-type work function layer to be deposited over the anti-reaction layer, thereby reducing gate resistance and providing a threshold voltage boost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate electrode structure is used, then the manufacturing process is simpler, but the gate resistance is high and threshold voltage boost is not achieved
Solution Approach 1:
The gate electrode is segmented into multiple functional layers: a base gate electrode layer, an intermediate layer, and a cap layer. Each layer serves a specific function - the base layer provides structural support, the intermediate layer enables selective deposition, and the cap layer reduces gate resistance and provides threshold voltage boost. This segmentation resolves the contradiction by achieving improved gate electrode performance through functional division while managing the increased structural complexity.
Solution Approach 2:
The gate electrode structure uses composite materials with different properties stacked together. The intermediate layer is composed of materials with specific deposition characteristics that allow selective metal cap layer formation. The cap layer uses materials optimized for low resistance. This composite structure resolves the contradiction by combining materials with complementary properties to achieve superior gate electrode performance.
2Reliability
If the metal cap layer is deposited uniformly, then the deposition process is simpler, but the gate resistance cannot be reduced effectively and threshold voltage boost is not achieved
Solution Approach 1:
The intermediate layer acts as a mediator between the base gate electrode and the metal cap layer. It has specific properties that enable selective deposition of the metal cap layer only in regions where gate resistance reduction and threshold voltage boost are needed. This intermediary layer resolves the contradiction by facilitating complex selective deposition while maintaining manufacturing feasibility through controlled material properties.
Solution Approach 2:
The metal cap layer is deposited selectively in specific regions rather than uniformly across the entire gate electrode. The intermediate layer enables this local quality approach by providing different deposition characteristics in different areas. This resolves the contradiction by achieving effective gate resistance reduction through localized metal cap formation while managing deposition process complexity through spatially selective manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by reducing gate resistance and enhancing the threshold voltage, leading to better integration density and efficiency in semiconductor devices.
Implementation Method 1
the anti-reaction layer is used to impede the selective deposition of the metal cap layer
Data Source
AI summary
Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.