Semiconductor Gate Structure With Silicon Soak Diffusion Barrier

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, the diffusion of n-type work function tuning material into p-type devices causes undesirable performance issues, necessitating a solution to minimize this diffusion.

Innovation Solution

A silicon soak process is applied to modify the surface properties of the p-type work function tuning layer, reducing the formation of n-type work function tuning material and minimizing its diffusion into the underlying layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but diffusion of n-type work function tuning material into p-type devices causes undesirable performance issues

Engineering Contradiction:

Improveintegration densityVSAvoiddevice performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A silicon-containing layer is deposited between the n-type work function tuning layer and the p-type work function tuning layer to act as a diffusion barrier. This intermediary layer prevents n-type material from diffusing into the p-type device while allowing the integration density improvements to continue.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The harmful diffusion process is extracted and blocked by introducing a separate barrier layer. The silicon-containing layer is specifically designed to stop the diffusion of n-type work function tuning material, separating the n-type and p-type devices and preventing the performance-degrading interaction.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If a diffusion barrier is introduced to prevent n-type material diffusion, then device performance is improved, but process complexity increases

Engineering Contradiction:

Improvedevice performanceVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The deposition parameters are optimized to form an ultra-thin silicon-containing layer (approximately 1-5 nm) that provides effective diffusion blocking with minimal impact on subsequent processing. The thin nature of the barrier layer allows it to be integrated into existing process flows without significantly increasing complexity.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces undesirable performance issues in p-type devices by minimizing the diffusion of n-type work function tuning material, thereby enhancing device performance and reliability.

Implementation Method 1

exposing the p-type work function tuning layer to a silicon-based precursor for a duration of time

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS20250338599A1Semiconductor gate structure and methods of forming the same

Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes depositing a gate dielectric layer on a first channel region; depositing a p-type work function tuning layer on the gate dielectric layer; exposing the p-type work function tuning layer to a silicon-based precursor for a duration of time; and depositing a n-type work function tuning layer on the p-type work function tuning layer. Exposing the p-type work function tuning layer to the silicon-based precursor can form a silicon-containing layer on the p-type work function tuning layer.