Semiconductor gate structure and methods of forming the same

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, the diffusion of n-type work function tuning material into p-type devices causes undesirable performance issues, necessitating a solution to minimize this diffusion.

Innovation Solution

A silicon soak process is applied to modify the surface properties of the p-type work function tuning layer, reducing the formation of n-type work function tuning material and minimizing its diffusion into the underlying layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If n-type work function tuning material is deposited to improve device performance, then device functionality is enhanced, but diffusion into p-type devices causes harmful effects

Engineering Contradiction:
Improvedevice performanceVSAvoidmaterial diffusion
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

An intermediate layer is introduced between the n-type work function tuning material and the p-type device structure. This intermediate layer acts as a diffusion barrier that prevents n-type material from migrating into the p-type device, thereby eliminating the harmful diffusion effect while allowing the n-type material to maintain its intended function of tuning work properties.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The work function tuning structure is segmented into distinct layers with different functional properties. By dividing the tuning material into separate segments or layers, the patent creates controlled interfaces that prevent unwanted diffusion while maintaining the electrical tuning functionality in specific regions.

Inventive Principle:
Principle #1Segmentation

2Productivity

If feature size is reduced to increase integration density, then more components fit in given area, but additional manufacturing and performance problems arise

Engineering Contradiction:
Improveintegration densityVSAvoidmanufacturing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent modifies material parameters such as composition, thickness, and deposition conditions of the work function tuning layers to optimize performance at reduced feature sizes. By adjusting these parameters, the invention maintains effective diffusion barriers and tuning functionality even as device dimensions shrink to increase integration density.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces undesirable performance issues in p-type devices by minimizing the diffusion of n-type work function tuning material, thereby enhancing device performance and reliability.

Implementation Method 1

exposing the p-type work function tuning layer to a silicon-based precursor

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 2

forming a silicon-containing layer on the first work function tuning layer... reducing the growth of the second work function tuning layer on the first work function tuning layer

Methodology Applied
Scientific EffectDiffusion Barrier: Diffusion Barrier

Data Source

PatentUS20250351541A1Semiconductor gate structure and methods of forming the same
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250351541A1 patent drawing
  • US20250351541A1 patent drawing
  • US20250351541A1 patent drawing

AI summary

A method includes depositing a gate dielectric layer on a first channel region; depositing a p-type work function tuning layer on the gate dielectric layer; exposing the p-type work function tuning layer to a silicon-based precursor for a duration of time; and depositing a n-type work function tuning layer on the p-type work function tuning layer. Exposing the p-type work function tuning layer to the silicon-based precursor can form a silicon-containing layer on the p-type work function tuning layer.