Semiconductor Gate Structures for Multi-Threshold FET Fabrication
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing field effect transistors (FETs) with different threshold voltages on the same substrate due to constraints in work function metal (WFM) layer thicknesses, particularly in gate-all-around (GAA) FETs and finFETs, which complicates the scaling down process and increases manufacturing complexity.
Innovation Solution
The proposed solution involves forming FET gate structures with different effective work function (EWF) values by varying the thickness of barrier metal layers between the WFM layers and high-K gate dielectric layers, using WFM oxide layers that induce dipole layers, allowing for the adjustment of threshold voltages without changing the WFM layer thicknesses, enabling the production of N-type and P-type FETs with similar WFM layer thicknesses but distinct threshold voltages on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the thickness of work function metal (WFM) layer is varied to achieve different threshold voltages, then multiple threshold voltages can be obtained, but the manufacturing complexity and constraints increase particularly in gate-all-around (GAA) FETs and finFETs
Solution Approach 1:
The patent applies local quality by varying the thickness of barrier metal layers at different locations within the gate structure. Specifically, different barrier metal layer thicknesses are used between the WFM layers and high-K gate dielectric layers to achieve different effective work function values, thereby producing FETs with different threshold voltages on the same substrate without changing the WFM layer thicknesses
Solution Approach 2:
The patent changes the parameter of barrier metal layer thickness to adjust the effective work function (EWF) values. By tuning the barrier metal layer thicknesses, the patent achieves different threshold voltages for N-type and P-type FETs while maintaining similar WFM layer thicknesses, thus reducing manufacturing constraints and complexity
2Ease of manufacture
If the WFM layer thickness is kept similar for both N-type and P-type FETs, then manufacturing complexity is reduced, but the ability to achieve different threshold voltages is compromised
Solution Approach 1:
The patent makes different parts of the gate structure have different functions by varying the barrier metal layer thicknesses locally. This allows N-type and P-type FETs to have similar WFM layer thicknesses (ease of manufacture) while achieving different threshold voltages through the differentiated barrier metal layer configurations
Solution Approach 2:
The barrier metal layers act as intermediaries between the WFM layers and high-K gate dielectric layers. By adjusting the thickness of these intermediary barrier metal layers, the patent achieves different effective work function values and threshold voltages without needing to change the WFM layer thicknesses, thus maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reliable fabrication of FETs with lower gate resistance and smaller dimensions, achieving multiple threshold voltages on a single substrate with reduced manufacturing complexity and cost, by tuning the barrier metal layer thicknesses to adjust the EWF values and threshold voltages of N-type and P-type FETs.
Implementation Method 1
using WFM oxide layers that induce dipole layers, allowing for the adjustment of threshold voltages without changing the WFM layer thicknesses
Data Source
AI summary
A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes first and second pair of source/drain regions disposed on a substrate, first and second nanostructured channel regions, and first and second gate structures with effective work function values different from each other. The first and second gate structures include first and second high-K gate dielectric layers, first and second barrier metal layers with thicknesses different from each, first and second work function metal (WFM) oxide layers with thicknesses substantially equal to each other disposed on the first and second barrier metal layers, respectively, a first dipole layer disposed between the first WFM oxide layer and the first barrier metal layer, and a second dipole layer disposed between the second WFM oxide layer and the second barrier metal layer.