Gate Substitution for IC Power and Timing Optimization
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Solution Overview
Problem
Existing methods for reducing leakage power in integrated circuit design face challenges such as inaccuracy in analytical models, high computational complexity, and inability to converge to optimal solutions, particularly in large designs like complex microprocessors, while also struggling to balance timing improvements with power increases.
Innovation Solution
A method that prioritizes gate swapping based on benefit counts and incremental slack propagation to minimize leakage power, avoiding extensive memory and run-time complexity by focusing on local and global impacts, and accounting for process variations to optimize timing and power trade-offs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If mathematical programming with accurate analytical models is used, then power and timing optimization accuracy is improved, but computational complexity and run time increase excessively
Solution Approach 1:
The patent segments the gate swapping optimization into distinct phases: initial timing analysis to identify critical paths, selective gate swapping on those paths, and iterative refinement. This divides the complex global optimization problem into manageable local decisions, reducing computational complexity while maintaining accuracy on critical timing paths.
Solution Approach 2:
The patent applies local quality by focusing optimization efforts specifically on timing-critical paths rather than uniformly optimizing all gates. Gates on critical paths receive detailed analysis and selective swapping, while non-critical gates are handled differently, allocating computational resources where they provide maximum benefit.
2Reliability
If dynamic programming is used for gate swapping, then optimization convergence is improved, but memory requirements and computational intractability increase for high fan-out situations
Solution Approach 1:
The patent extracts and removes gates from critical timing paths for swapping to alternative implementations with different power-delay characteristics. By identifying and isolating specific gates on critical paths, the method avoids the need to analyze all high fan-out situations simultaneously, reducing memory requirements while maintaining convergence on the extracted critical elements.
3Loss of energy
If leakage power reduction is prioritized in timing non-critical parts, then leakage power is reduced, but new timing violations may be created
Solution Approach 1:
The patent performs preliminary timing analysis to establish baseline timing paths and identify critical paths before attempting leakage reduction. This preliminary characterization ensures that subsequent power optimization actions do not create timing violations, as the critical paths are already identified and protected from aggressive optimization.
Solution Approach 2:
The patent applies partial action by selectively optimizing only non-critical paths for leakage reduction while leaving critical paths untouched or minimally modified. This partial optimization approach reduces leakage power in safe areas without risking timing violations on critical paths.
4Speed
If timing improvement is prioritized in critical parts, then timing is improved, but leakage power increases
Solution Approach 1:
The patent changes parameters by selecting alternative gate implementations with different power-delay trade-offs. For gates on critical paths, it selects alternatives that improve timing even if leakage increases, while for non-critical paths it selects alternatives that reduce leakage even if timing degrades slightly. This parameter-based selection resolves the contradiction by applying different optimization goals to different path categories.
Data Source
AI summary
A processing device can identify gates of an integrated circuit design having a slack value less than a predefined slack threshold. The processing device can further, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The processing device can still further swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.