Gate Structure Support Pattern Layout to Prevent CMP Dishing
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Solution Overview
Problem
In semiconductor manufacturing, the dishing phenomenon occurs during planarization, where areas of different density are polished at different rates, leading to a concave profile that affects component quality.
Innovation Solution
A semiconductor structure with supporting patterns arranged perpendicular to the current direction is formed to prevent dishing, using insulating materials like silicon oxide, which are integrated into the gate structure to maintain current flow paths without hindrance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planarization (CMP) is used to flatten the surface, then surface flatness is improved, but dishing phenomenon occurs causing concave profiles in low-density areas
Solution Approach 1:
The patent applies local quality by introducing supporting patterns specifically in low-density areas where dishing occurs. These patterns are formed by selectively removing material in certain regions and replacing it with supporting structures, creating non-uniform local properties that counteract the dishing effect during CMP while maintaining overall surface flatness.
Solution Approach 2:
The supporting patterns create an asymmetric structure within the gate, with additional material support in specific regions (where patterns are formed) versus regions without patterns. This asymmetric distribution of supporting material compensates for the asymmetric material removal that causes dishing in low-density areas during planarization.
2Shape
If supporting patterns are formed in the gate to prevent dishing, then gate profile is improved, but current flow path may be hindered
Solution Approach 1:
The supporting patterns are segmented into discrete, separated structures rather than continuous blocks. This segmentation allows current to flow through the spaces between the patterns, reducing electrical hindrance while still providing sufficient structural support to prevent dishing during planarization.
Solution Approach 2:
The supporting patterns are designed with partial coverage - not the entire gate area is filled with supporting material. Instead, patterns are strategically placed in specific regions where dishing is most problematic, providing just enough support to prevent dishing while minimizing interference with current flow paths.
Data Source
AI summary
The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a gate structure which extends along a first direction, and a plurality of supporting patterns which are separated from each other and arranged along a second direction which is perpendicular to the first direction.