Semiconductor Gate Structure Supporter to Prevent Peeling
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Solution Overview
Problem
The current manufacturing process for semiconductor devices with low line width gate structures requires multiple wet cleaning processes, leading to peeling issues that affect the electrical properties of the gate structure due to its small critical dimension and large height.
Innovation Solution
A method involving the formation of a multilayer film stack on a substrate, followed by the creation of a supporter that penetrates and extends along the top of the gate structures, effectively improving the depth-to-width ratio and preventing peeling during cleaning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple wet cleaning processes are used to manufacture gate structures with small critical dimensions, then cleaning effectiveness is improved, but gate structure peeling occurs affecting electrical properties
Solution Approach 1:
The method performs preliminary actions by forming the complete multilayer film stack and supporter structure before the etching process that defines the final gate structure dimensions. The supporter is established in advance to provide structural reinforcement throughout subsequent manufacturing steps, preventing peeling during cleaning operations while maintaining precise dimensional control of the gate structure.
Solution Approach 2:
The supporter acts as an intermediary element between the substrate and the gate structure. It provides mechanical support and stress distribution, mediating the forces that would otherwise cause peeling during wet cleaning processes. The supporter's material properties and structural design enable it to bear the mechanical stresses while allowing the gate structure to maintain its precise dimensions and electrical properties.
2Productivity
If gate structure critical dimension is reduced for high integration density, then device integration is improved, but gate structure becomes prone to peeling during cleaning
Solution Approach 1:
The invention addresses the fragility of reduced-dimension gate structures by introducing a vertical dimension through the supporter structure. While the gate structure's horizontal critical dimensions are reduced for high integration density, the supporter extends vertically to provide reinforcement, effectively transferring the stability requirement from the horizontal plane to the vertical plane. This dimensional transition allows small critical dimensions without sacrificing structural reliability.
Solution Approach 2:
The method employs composite material strategies by combining the gate structure with the supporter in a multilayer configuration. The supporter is formed from materials with appropriate mechanical properties that complement the gate structure materials, creating a composite system where the overall reliability exceeds that of the individual components. This composite approach enables high integration density while maintaining gate structure stability through material synergies.
Data Source
AI summary
A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate; forming a multilayer film stack on the substrate; forming a supporter at a top of the multilayer film stack; and etching the multilayer film stack to form a plurality of gate structures arranged at intervals along a first direction, where the supporter penetrates a top of each of the plurality of gate structures and extends along the first direction.