Gate Tap Extension for Semiconductor Mask Design
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Solution Overview
Problem
In semiconductor device manufacturing, the miniaturization of transistors leads to challenges in maintaining gate width consistency, particularly at the boundary areas where HEIP phenomena occur, making it difficult to prevent errors during the photo process due to optical proximity effects.
Innovation Solution
A method of designing a mask that extends the gate tap outside the active region to contact another gate structure or tap, ensuring a wider width and performing optical proximity correction (OPC) to replace small gate structure portions with larger gate tap portions, thereby preventing errors during mask manufacturing rule checking and ensuring process margin during gate formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate width is reduced to achieve transistor miniaturization, then the transistor size is reduced, but the gate width consistency at boundary areas deteriorates due to HEIP phenomenon and optical proximity effects
Solution Approach 1:
The patent applies preliminary action by extending the gate tap structure outside the active region before the photo process. This pre-configuration ensures that during photolithography, the gate structure maintains sufficient width and process margin, preventing errors that would otherwise occur due to optical proximity effects in miniaturized transistors.
Solution Approach 2:
The patent applies local quality by creating different gate structure configurations in different regions. Specifically, the gate tap is extended in boundary areas where HEIP phenomenon occurs, while maintaining standard gate structures in central regions. This localized modification addresses the specific manufacturing precision issues at boundaries without affecting the overall miniaturization benefits.
2Reliability
If the gate tap is extended outside the active region, then the process margin is improved, but the device complexity increases
Solution Approach 1:
The patent merges the gate structure with the gate tap by extending them as a continuous structure outside the active region. This integration simplifies the overall design compared to separate components, while still providing the benefits of extended process margin and reduced optical proximity effects.
3Manufacturing precision
If OPC is performed to replace small gate structure portions with larger gate tap portions, then the manufacturing precision is improved, but the computational time and complexity increase
Solution Approach 1:
The OPC process performs preliminary action by pre-calculating and replacing small gate structure portions with larger gate tap portions before mask fabrication. This advance preparation ensures that the final mask design has sufficient process margin and avoids errors during photolithography, while the automated OPC algorithm efficiently manages the computational complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that the gate structures are formed with sufficient process margin, preventing errors and maintaining the required width standards, thus addressing the HEIP phenomenon and ensuring reliable transistor performance.
Implementation Method 1
when an OPC for offsetting the optical proximity effect generated during a photo process in which a photoresist pattern is formed using the designed mask is performed
Data Source
AI summary
In a method of designing a mask, a first mask including an active region, a gate structure, and a gate tap partially overlapping the active region and the gate structure is designed. The first mask is changed so that a portion of the gate tap is extended. An OPC is performed on the changed first mask to design a second mask.