Gate Structure Thickness Tuning at Active-Isolation Interfaces
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Solution Overview
Problem
The manufacturing of transistors with different operation voltages on the same wafer or chip is complicated, leading to increased costs and reduced yield due to the complexity of the manufacturing process.
Innovation Solution
A method is introduced where a part of the capping layer above the interface between the active region and the isolation structure is removed, reducing the thickness of the gate structure at this interface, thereby simplifying the process and enhancing manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure is formed with uniform thickness over the isolation structure and active region, then the manufacturing process is simpler, but the protruding gate surface causes damage in subsequent processes and reduces manufacturing yield
Solution Approach 1:
The patent applies local quality by removing the capping layer selectively at the interface region between the active region and isolation structure, creating a localized thickness reduction only where needed. This allows the gate structure to have different effective thicknesses in different regions - thinner at the interface to prevent protrusion damage, and maintained thickness over the active region for proper transistor operation.
2Adaptability or versatility
If transistors for different operation voltages are formed on the same wafer, then device versatility is improved, but the manufacturing process becomes complicated and manufacturing yield decreases
Solution Approach 1:
The patent applies universality by creating a single gate structure design that can serve multiple functions - supporting both high-voltage and low-voltage transistor operations on the same wafer. The selective capping layer removal enables the same gate structure to accommodate different voltage requirements without requiring separate manufacturing processes for different device types.
Data Source
AI summary
A manufacturing method of a gate structure includes the following steps. A semiconductor substrate is provided. An isolation structure is formed in the semiconductor substrate and surrounds an active region in the semiconductor substrate. A gate pattern is formed on the active region and the isolation structure. The gate pattern includes a first gate structure and a first capping layer disposed on the first gate structure. A part of the first capping layer located above an interface between the active region and the isolation structure is removed for exposing a part of the first gate structure located above the interface between the active region and the isolation structure. A removing process is performed for reducing a thickness of the part of the first gate structure located above the interface between the active region and the isolation structure.