Gate Tie-Down With Inner Spacer Prevents Shorts
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Solution Overview
Problem
Conventional gate tie-down structures in CMOS processing often result in shorts between silicide regions of source/drain areas and adjacent gate conductive materials due to the close proximity and small margins of dielectric materials, leading to chip area loss and design inefficiencies.
Innovation Solution
A method involving the formation of inner spacers and trench contacts on gate structures, with a self-aligned conductive material connecting the gate contact to the trench contact, allowing the gate contact to 'fly' over the source/drain contact, thereby preventing shorts and optimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate contacts are formed in STI regions with conventional gate tie-down structures, then chip area is reduced, but shorts occur between silicide regions and adjacent gate conductive materials due to close proximity
Solution Approach 1:
An inner spacer is introduced as an intermediary dielectric structure positioned between the gate contact and the trench silicide contact. This inner spacer acts as a mediator that provides additional electrical isolation, preventing shorts while enabling the gate contact to be positioned closer to the source/drain region, thus reducing chip area.
Solution Approach 2:
The solution moves from a two-dimensional planar isolation approach to a three-dimensional structured isolation by forming the inner spacer that extends vertically and horizontally between the gate contact and trench contact. This dimensional change allows for better spatial separation of conductive elements while maintaining compact layout.
2Area of stationary object
If gate contacts are positioned close to source/drain regions to save chip area, then chip area is reduced, but the margins of dielectric materials become too small causing shorts
Solution Approach 1:
The inner spacer serves as an intermediary structure that compensates for reduced dielectric margins. By introducing this additional dielectric layer between the gate contact and trench contact, the effective isolation distance is increased even when the overall layout is compact, thus maintaining manufacturing precision requirements.
Solution Approach 2:
The dielectric isolation is segmented into multiple parts: the standard ILD layer and the additional inner spacer structure. This segmentation allows the isolation function to be distributed across multiple dielectric layers, providing better control over electrical margins while maintaining compact dimensions.
3Area of stationary object
If conventional gate tie-down structures are used with small dielectric margins, then chip area is saved, but shorts occur between adjacent conductive bodies
Solution Approach 1:
The inner spacer is positioned as an intermediary structure between the gate contact and the trench silicide contact, providing an additional dielectric barrier that prevents harmful electrical shorts. This mediator structure ensures that even when conductive bodies are in close proximity, sufficient electrical isolation is maintained.
Solution Approach 2:
The inner spacer is formed in advance during the fabrication process to preemptively prevent shorts before they can occur. By establishing this additional isolation structure during manufacturing, the design proactively counteracts the potential harmful effect of close proximity between conductive elements.
Data Source
AI summary
A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.