Gate Tie-Down Link Structure for Uniform Grid Gate and Contact Cuts

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Solution Overview

Problem

The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the constraints on lithographic processes used to pattern features, leading to a trade-off between critical dimension and spacing.

Innovation Solution

The implementation of a unified dielectric cut plug process for trench contact and metal gate cuts, followed by conductive link formation to reconnect isolated structures, simplifies the fabrication process and reduces process variation, while ensuring robustness and cost-effectiveness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If device dimensions are scaled down to increase density, then capacity increases, but manufacturing precision deteriorates due to lithographic constraints

Engineering Contradiction:
Improvedevice densityVSAvoidlithographic patterning precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent segments the gate structure into multiple sections with tie-down links connecting them, allowing each segment to be patterned independently within lithographic constraints while maintaining overall gate continuity through the conductive tie-down links that extend into source/drain regions

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extends the gate structure vertically into the source and drain regions, moving from a planar 2D gate configuration to a 3D structure that utilizes the vertical dimension to maintain gate control and connectivity without requiring tighter lateral spacing

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If feature spacing is reduced to increase density, then device capacity increases, but process variation increases leading to performance degradation

Engineering Contradiction:
Improvedevice capacityVSAvoidprocess variation control
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent merges the gate structure with the source and drain regions through conductive tie-down links, creating an integrated structure where variations in gate spacing are compensated by the continuous conductive path that extends into the source/drain regions, thereby reducing the impact of process variation on overall device performance

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If conventional separate patterning processes are used for gate and trench contact cuts, then manufacturing flexibility is maintained, but process complexity and cost increase

Engineering Contradiction:
Improveprocess flexibilityVSAvoidfabrication process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent creates a universal tie-down link structure that serves multiple functions: it provides gate segment connectivity, establishes electrical contact with source/drain regions, and enables a unified patterning approach for both gate and trench contact cuts, thereby simplifying the overall fabrication process while maintaining manufacturing flexibility

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250301729A1Integrated circuit structures having gate tie-down links for uniform grid metal gate and trench contact cut
Publication Date: 2025.09.25 INTEL CORP
  • US20250301729A1 patent drawing
  • US20250301729A1 patent drawing
  • US20250301729A1 patent drawing

AI summary

Integrated circuit structures having gate tie-down links for uniform grid metal gate and trench contact cut are described. A structure includes a dielectric sidewall spacer between a gate electrode and a conductive trench contact. First and second parallel dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A recess is in the gate electrode, the conductive trench contact and the dielectric sidewall spacer. A conductive link is in the recess, the conductive link electrically connecting the gate electrode and the conductive trench contact.