Gate-Top Dielectric Structure for Low-Capacitance Self-Aligned Contacts
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Solution Overview
Problem
Existing self-aligned contact formation processes for multi-gate transistors face challenges such as increased parasitic capacitance and electrical shorts due to the use of high-k dielectric materials and breaching of gate spacer layers, which affect the reliability and yield of semiconductor devices.
Innovation Solution
The use of a capping dielectric layer with a dielectric constant between 3.9 and 10, combined with a planarization process to form coplanar surfaces, reduces parasitic capacitance and enhances yield by ensuring precise alignment of source/drain contacts in multi-gate transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric material is used for the capping dielectric layer, then the gate control is improved, but the parasitic capacitance increases
Solution Approach 1:
The patent applies different dielectric materials with different k-values to different regions: high-k dielectric (k>10) is used specifically in the gate structure region where gate control is needed, while lower-k dielectric material (k<10) is used for the capping dielectric layer to minimize parasitic capacitance. This spatial differentiation of material properties resolves the contradiction between improving gate control and reducing parasitic capacitance.
Solution Approach 2:
The dielectric structure is segmented into multiple functional layers: the gate dielectric layer (with high-k material) separate from the capping dielectric layer (with lower-k material). This segmentation allows each layer to independently fulfill its function - the gate dielectric provides strong gate control while the capping dielectric minimizes parasitic capacitance, thus resolving the technical contradiction.
2Ease of manufacture
If the recess is defined in gate spacer layers, then the self-aligned contact formation is enabled, but electrical shorts occur due to breaching of gate spacer layers
Solution Approach 1:
The patent introduces a contact etch stop layer (CESL) as an intermediary protective layer between the gate spacer layers and the source/drain contact openings. The CESL prevents direct breaching of the gate spacer layers during contact formation, thereby eliminating electrical shorts while still enabling self-aligned contact formation through the recess in the gate spacer layers.
Solution Approach 2:
The contact etch stop layer is deposited beforehand to provide protective cushioning over the gate spacer layers. This pre-established protective layer prevents harmful effects (electrical shorts) before they can occur during the subsequent contact formation process, allowing self-aligned contacts to be formed without breaching the gate spacer layers.
3Ease of manufacture
If the gate structure is recessed to form a recess, then the self-aligned capping layer formation is enabled, but the manufacturing complexity increases
Solution Approach 1:
The gate structure is recessed beforehand to form a recess that serves as a pre-prepared cavity for receiving the capping dielectric layer. This preliminary action of recessing the gate structure enables the subsequent self-aligned formation of the capping layer without requiring additional alignment steps, thus reducing overall manufacturing complexity despite the initial recessing step.
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes an active region having a channel region and a source/drain region, a gate structure over the channel region, a gate spacer layer disposed over the channel region and extending along a sidewall of the gate structure, an epitaxial source/drain feature over the source/drain region, a contact etch stop layer (CESL) disposed on the epitaxial source/drain feature and extending along a sidewall of the gate spacer layer, a source/drain contact disposed over the epitaxial source/drain feature, and a dielectric cap layer disposed over the gate structure, the gate spacer layer and at least a portion of the CESL. A sidewall of the source/drain contact is in direct contact with a sidewall of the CESL.