Gate Trench Capacitance Layout for Power Transistor ESD Ruggedness
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Solution Overview
Problem
Small-area semiconductor dies are susceptible to electrostatic discharge (ESD) due to their smaller gate pad area, requiring additional space- and cost-intensive ESD diode circuits for improved ruggedness.
Innovation Solution
Incorporating a gate trench arrangement under the gate pad on the semiconductor die substrate, which increases the effective gate pad area and input capacitance, enhancing ESD ruggedness without the need for additional ESD diode circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate pad area is increased to improve ESD ruggedness, then the ESD ruggedness is improved, but the die area increases
Solution Approach 1:
The patent extends the gate pad structure vertically into the substrate by forming trenches that penetrate through the substrate thickness. This three-dimensional extension increases the effective gate pad area without increasing the planar die area, thereby improving ESD ruggedness while maintaining a compact footprint.
Solution Approach 2:
The gate pad structure is nested within the substrate by forming trenches that extend into the substrate material. The gate electrode is positioned within these trenches, creating a nested configuration where the gate structure is embedded in the substrate rather than occupying additional planar space.
2Reliability
If additional ESD diodes are added to improve ESD ruggedness, then the ESD ruggedness is improved, but the device complexity and cost increase
Solution Approach 1:
The gate pad structure serves multiple functions: it provides the gate control function for the power transistor and simultaneously provides ESD protection functionality. By making the gate pad multi-functional, the patent eliminates the need for separate ESD diodes, reducing device complexity while maintaining ESD ruggedness.
Solution Approach 2:
The patent merges the gate pad function with the ESD protection function into a single integrated structure. The gate electrode and pad are combined with ESD diode functionality, creating a unified structure that performs both gate control and ESD protection without requiring separate components.
3Reliability
If the gate pad area is increased to improve ESD ruggedness, then the ESD ruggedness is improved, but the input capacitance increases
Solution Approach 1:
The patent increases the effective gate pad area by extending into the substrate dimension through trenches. This vertical extension provides additional capacitance area without proportionally increasing the planar footprint, thereby improving ESD ruggedness while controlling the overall input capacitance increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased input capacitance enhances ESD ruggedness, particularly for human body model (HBM) scenarios, allowing smaller dies to be driven by standard drivers and reducing electromagnetic interference while maintaining efficient switching performance.
Implementation Method 1
the plurality of additional gate trenches including additional gate electrodes that are capacitively coupled to the semiconductor substrate and increase the input capacitance of the power transistor
Implementation Method 2
the ESD (electrostatic discharge) ruggedness capability of the die (chip) correlates with the input capacitance of the chip
Data Source
AI summary
A semiconductor die includes: a semiconductor substrate; transistor cells formed in a first region of the semiconductor substrate and electrically coupled in parallel to form a power transistor, the transistor cells including first trenches that extend from a first surface of the semiconductor substrate into the first region; a gate pad formed above the first surface and electrically connected to gate electrodes in the first trenches, the gate pad being formed over a second region of the semiconductor substrate that is devoid of functional transistor cells; second trenches extending from the first surface into the second region and including gate electrodes that are electrically connected to the gate pad and form a first conductor of an additional input capacitance of the power transistor; and a second conductor of the additional input capacitance formed in the second region adjacent the second trenches. Methods of producing the semiconductor die are also described.