Gate Trench Etch-Back Uniformity Across Varying Widths

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Solution Overview

Problem

The challenge in integrated circuit manufacturing is achieving uniformity in gate trench widths across varying dimensions, which affects transistor performance due to etch variability and micro-trenching issues, particularly in high aspect ratio and pattern density applications, leading to recess differences and increased gate resistance.

Innovation Solution

The implementation of an inductively coupled plasma (ICP) etch tool with pulsing plasma capabilities using H2/N2/CH4 and He gases, along with SO2 for passivation, to achieve a uniform etch back process, reducing recess variability from 20 nm to less than 2 nm, and employing a common metal gate flow to address multi-VT requirements in gate-all-around architectures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etch processes are used on high aspect ratio structures with varying gate trench widths, then etch variability and micro-trenching occur, but achieving uniform etch back across different trench widths becomes difficult

Engineering Contradiction:
Improveuniformity of gate trench widthsVSAvoidcomplexity of etch process control
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies periodic action by implementing a multi-stage etch process with alternating plasma conditions. The process uses different gas flows (H2/N2/CH4 and He) in alternating phases to periodically adjust etch rate and profile control, enabling uniform etch back across trenches of varying widths while maintaining high aspect ratio integrity.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements parameter changes by dynamically adjusting plasma power, gas composition, and pressure during the etch process. These parameter modifications allow the etch process to adapt to different trench geometries, achieving uniform etch back across varying gate trench widths while controlling micro-trenching and surface roughness.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If feature dimensions are scaled down to increase device density, then transistor capacity increases, but etch variability and micro-trenching worsen

Engineering Contradiction:
Improvedevice densityVSAvoiduniformity of gate trench widths
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The periodic alternation of plasma conditions during etching provides continuous adjustment capability, ensuring uniform etch back even as feature dimensions scale down to sub-10nm nodes. This periodic control mechanism maintains manufacturing precision while enabling increased device density through smaller features.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The etch process incorporates real-time monitoring and feedback control of etch rate and profile. This feedback mechanism allows dynamic adjustment of process parameters to compensate for variations at scaled dimensions, maintaining uniform gate trench widths despite the challenges of high-density patterning.

Inventive Principle:
Principle #23Feedback

3Reliability

If multi-gate and nanowire transistors are fabricated to improve short channel control, then device performance improves, but lithographic process constraints increase

Engineering Contradiction:
Improveshort channel controlVSAvoidlithographic process constraints
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the gate structure into multi-gate or nanowire configurations. This segmentation approach improves short channel control by creating multiple gate interfaces, while the uniform etch back process manages the resulting complexity by ensuring consistent dimensional control across all segmented structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar to three-dimensional gate structures (multi-gate and nanowire). This dimensional change enhances short channel control by wrapping the gate around the channel, and the uniform etch back process manages the complexity by providing consistent dimensional control in all spatial dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Manufacturing precision

If uniform etch back is achieved across varying trench widths, then surface roughness decreases, but process control complexity increases

Engineering Contradiction:
Improveuniformity of gate trench widthsVSAvoidcomplexity of process control
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The periodic alternation of plasma conditions creates a self-regulating etch process that naturally achieves uniform etch back across varying trench widths. This periodic action reduces surface roughness by continuously adjusting etch rate, while the systematic nature of the periodic cycles manages process control complexity through repeatable patterns.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The systematic modification of process parameters (gas composition, power, pressure) during etching achieves uniform etch back and reduced surface roughness. These controlled parameter changes manage complexity by using well-defined parameter transitions rather than arbitrary adjustments.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in improved uniformity and reduced surface roughness, enhancing transistor performance by minimizing etch variability and micro-trenching, while enabling tight N-P boundary control and high transistor density in gate-all-around architectures.

Implementation Method 1

The implementation of an inductively coupled plasma (ICP) etch tool with pulsing plasma capabilities

Methodology Applied
Scientific EffectInductive coupling: Electromagnetic Induction

Implementation Method 2

using H2/N2/CH4 and He gases, along with SO2 for passivation, to achieve a uniform etch back process

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 3

along with SO2 for passivation, to achieve a uniform etch back process, reducing recess variability from 20 nm to less than 2 nm

Methodology Applied
Scientific EffectChemical passivation: Adsorption

Data Source

PatentUS20240178227A1Fabrication of integrated circuit structures having uniformity among varying gate trench widths
Publication Date: 2024.05.30 INTEL CORP
  • US20240178227A1 patent drawing
  • US20240178227A1 patent drawing
  • US20240178227A1 patent drawing

AI summary

Integrated circuit structures having uniformity among varying gate trench widths are described. For example, an integrated circuit structure includes a first fin, and a first gate trench over the first fin, the first gate trench having a first width. The integrated circuit structure also includes a second fin, and a second gate trench over the second fin, the second gate trench having a second width greater than the first width. The integrated circuit structure also includes a gate electrode layer having a first portion along a bottom and partially along sidewalls of the first trench, and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench.