Multi-Gate Gate Trench Stack for Lower Leakage Current
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Solution Overview
Problem
Multi-gate transistors face challenges in reducing gate leakage current while maintaining conductive layer thickness, which affects the performance and integration density of semiconductor devices.
Innovation Solution
The semiconductor device incorporates two gate insulating layers with different materials in both PMOS and NMOS regions, with a conductive layer formed between these layers in the PMOS region, to reduce leakage current without thinning the conductive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-gate transistor is used to increase integration density, then current control capability is improved, but gate leakage current increases
Solution Approach 1:
The gate insulating layer is divided into two separate layers: a first gate insulating layer (e.g., SiO2) in contact with the active pattern, and a second gate insulating layer (e.g., high-k material) disposed on top. This segmentation allows each layer to perform different functions - the first layer provides good interface characteristics while the second layer provides high dielectric constant for better control, thereby reducing gate leakage current while maintaining the benefits of multi-gate transistor structure
Solution Approach 2:
The gate insulating structure uses composite materials by combining different dielectric materials with different properties. The first gate insulating layer uses a material with good interface characteristics (e.g., SiO2), while the second gate insulating layer uses a high-k material (e.g., HfO2, Ta2O5). This composite structure achieves both low interface trap density and high dielectric constant, effectively reducing gate leakage current while maintaining integration density
2Object-generated harmful factors
If the thickness of the conductive layer is reduced to decrease gate leakage, then gate control is improved, but device performance deteriorates
Solution Approach 1:
Instead of changing the thickness parameter of the conductive layer, the invention changes the dielectric constant parameter of the gate insulating layers. By using a high-k material for the second gate insulating layer, the dielectric constant is increased, which strengthens gate control and reduces leakage current without requiring thinning of the conductive layer, thereby preserving device performance
Solution Approach 2:
The two-layer gate insulating structure acts as an intermediary between the active pattern and the conductive layer. This intermediate structure provides both good interface characteristics (through the first layer) and high dielectric constant (through the second layer), enabling effective gate control and leakage reduction without directly affecting the conductive layer thickness or compromising device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively decreases gate leakage current while preserving the thickness of the conductive layer, enhancing the performance and integration density of semiconductor devices.
Implementation Method 1
a first gate insulating layer disposed along a sidewall and a bottom surface of the gate trench, a first conductive layer disposed on the first gate insulating layer inside the gate trench, a second gate insulating layer disposed on the first conductive layer inside the gate trench, and including a material different from a material of the first gate insulating layer
Data Source
AI summary
A semiconductor device includes a substrate, an active pattern disposed on the substrate and extending in a first horizontal direction, a gate spacer disposed along each of sidewalls of a gate trench on the active pattern and extending in a second horizontal direction different from the first horizontal direction, a first gate insulating layer disposed along a sidewall and a bottom surface of the gate trench, a first conductive layer disposed on the first gate insulating layer inside the gate trench, a second gate insulating layer disposed on the first conductive layer inside the gate trench, and including a material different from a material of the first gate insulating layer, a second conductive layer disposed on the second gate insulating layer inside the gate trench, and a third conductive layer disposed on the second conductive layer so as to fill a remaining inner space of the gate trench.