III-Nitride Transistors with Gate Trench for Normally-Off Operation
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Solution Overview
Problem
Existing III-nitride field effect transistors (FETs) operating in normally-off mode face challenges with higher on-resistance and lower output-current, requiring a solution that balances high threshold voltage, low on-resistance, and uniformity in threshold and on-resistance values.
Innovation Solution
A method of fabricating III-nitride transistors involving a 1-5 nanometer thick AlGaN barrier layer, a dielectric layer, and a gate trench etched through the barrier and dielectric layers with a gate insulator stack, including single-crystalline AlN and polycrystalline AlN layers, to achieve a normally-off operation with minimal on-resistance and high threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a normally-off mode operation is implemented in III-nitride FETs, then the threshold voltage is improved (higher), but the on-resistance increases (worsens)
Solution Approach 1:
The patent applies parameter changes by precisely controlling the barrier layer thickness (1-5 nm) and gate trench depth (0-5 nm into the channel layer) to optimize the balance between threshold voltage and on-resistance. By adjusting these dimensional parameters, the invention achieves normally-off operation with reduced on-resistance penalty compared to conventional approaches.
Solution Approach 2:
The invention implements local quality by creating a localized gate trench structure that extends into the channel layer only in specific regions, rather than uniformly throughout. This localized modification allows the gate to exert precise control over the channel conductivity, achieving high threshold voltage while maintaining low on-resistance in the remaining channel regions.
2Manufacturing precision
If the gate trench extends deeper into the channel layer, then the threshold voltage control is improved, but the on-resistance increases
Solution Approach 1:
The patent establishes an optimal parameter range for gate trench depth (0-5 nm into the channel layer) that balances threshold voltage control with on-resistance management. This precise parameter specification resolves the contradiction by identifying the sweet spot where sufficient gate control is achieved without excessive resistance penalty.
Solution Approach 2:
The invention applies partial action by having the gate trench extend only slightly into the channel layer (0-5 nm) rather than deeply throughout. This partial penetration provides just enough gate control for high threshold voltage while avoiding the excessive on-resistance that would result from deeper trench extension.
3Object-affected harmful factors
If a thin barrier layer (1-5 nm) is used, then the on-resistance is reduced, but the manufacturing precision required increases
Solution Approach 1:
The patent specifies a narrow but achievable thickness range (1-5 nm) for the barrier layer that minimizes on-resistance while remaining compatible with standard manufacturing capabilities. This parameter optimization resolves the contradiction by selecting a thickness that is thin enough to reduce resistance but thick enough to be manufacturable with acceptable precision.
Data Source
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Figure 3A~3C
AI summary
A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.