Gate Trench Structure With Oxidized Cap for Lower Floating Capacitance
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Solution Overview
Problem
In semiconductor memory devices like DRAM, the hybrid gate structure with a conductive material of small work function for the upper gate electrode embedded in a gate trench faces challenges in forming a flat top surface, leading to increased height towards the inner wall, which reduces the short margin with bit contact plugs and increases floating capacitance between bit and word lines.
Innovation Solution
A semiconductor device design where the upper gate electrode is made of a conductive material with a smaller work function, such as polycrystalline silicon, is embedded in the gate trench, and its surface is oxidized to form a thicker insulating film, which is then covered by a gate cap insulating film, resulting in a flat top surface and reduced floating capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a conductive material with small work function is used for the upper gate electrode to reduce GIDL, then GIDL is reduced, but the top surface of the gate electrode becomes non-flat and height increases toward the inner wall
Solution Approach 1:
The gate electrode is divided into two separate conductive material layers: a first conductive material layer (e.g., tungsten or titanium nitride with large work function) and a second conductive material layer (e.g., polycrystalline silicon with small work function). This segmentation allows each layer to perform its specific function independently, preventing the shape distortion that occurs when using only a small work function material.
Solution Approach 2:
The gate electrode uses a composite structure combining two different conductive materials with complementary properties. The first material provides structural stability and large work function characteristics, while the second material contributes small work function properties for GIDL reduction. This composite approach resolves the contradiction by integrating the benefits of both materials without the drawbacks of either used alone.
2Object-generated harmful factors
If the top surface of the gate electrode becomes higher toward the inner wall, then the hybrid gate structure is formed, but the short margin with bit contact plug is reduced
Solution Approach 1:
By segmenting the gate electrode into two material layers, the patent achieves GIDL reduction through the second material while the first material layer maintains a flatter profile that preserves adequate short margin with the bit contact plug, thus resolving the spatial conflict.
Solution Approach 2:
Different regions of the gate electrode have different material compositions optimized for different functions: the first conductive material layer provides structural foundation and work function control, while the second layer provides localized GIDL reduction. This local differentiation allows simultaneous optimization of both GIDL performance and spatial clearance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the short margin of bit contact plugs and reduces floating capacitance by ensuring a flat top surface of the gate electrode and using insulating films with lower permittivity, thereby improving the structural integrity and operational efficiency of the memory cell transistor.
Implementation Method 1
its surface is oxidized to form a thicker insulating film
Data Source
AI summary
Disclosed herein is a method that includes forming a gate trench in a semiconductor substrate, forming a gate insulating film on an inner wall of the gate trench, forming a gate electrode in the gate trench via the gate insulating film, ashing a top surface of the gate electrode to form a first insulating film, and forming a gate cap insulating film embedded in the gate trench to cover the first insulating film.