Gate Trench Planarization for Uniform Semiconductor Threshold Voltage
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Solution Overview
Problem
The challenge in manufacturing semiconductor devices is maintaining the uniformity of gate electrode height and threshold voltages across high and low density transistor areas, as existing methods often result in non-uniformity due to variations in sacrificial layer height and etching processes.
Innovation Solution
A method involving the formation of a sacrificial layer within gate trenches, followed by planarization and selective removal to create a uniform gate dielectric and work function metal patterns, ensuring the gate electrode height is maintained through protection of insulation patterns during CMP and etching processes, thereby controlling threshold voltages uniformly across different transistor densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing methods are used to manufacture gate electrodes, then manufacturing process is simpler, but gate electrode height uniformity deteriorates due to variations in sacrificial layer height and etching processes
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer before the gate electrode formation process. This planarization layer pre-compensates for height variations in the sacrificial layer, ensuring that subsequent etching processes produce uniform gate electrode heights. The planarization layer is formed in advance to create a flat surface that guides the etching depth, thereby resolving the uniformity issue without requiring complex real-time control during etching.
Solution Approach 2:
The patent introduces a planarization layer as an intermediary element between the sacrificial layer and the gate electrode formation process. This intermediary layer mediates the height variations by providing a uniform reference surface for etching, allowing the gate electrode height to be controlled uniformly across different regions. The planarization layer acts as a buffer that absorbs the variations from the sacrificial layer while maintaining the desired gate electrode dimensions.
2Reliability
If threshold voltages are controlled across different transistor densities, then device performance improves, but process control difficulty increases due to density variations
Solution Approach 1:
The patent applies local quality by forming region-specific gate electrodes with different heights tailored to the local transistor density requirements. High-density regions receive taller gate electrodes while low-density regions receive shorter gate electrodes, optimizing the threshold voltage control for each region. This localized approach allows precise control of threshold voltages according to the specific needs of each area, improving overall device reliability without requiring complex global control mechanisms.
Solution Approach 2:
The patent uses preliminary action by pre-forming the planarization layer before gate electrode formation, which enables subsequent region-specific etching processes. The planarization layer is prepared in advance to provide a uniform baseline, allowing the etching process to create different gate electrode heights in different regions based on the sacrificial layer configuration. This preliminary preparation simplifies the control of threshold voltages across varying densities by establishing a consistent reference point before regional differentiation.
3Ease of manufacture
If sacrificial layer height varies in different regions, then manufacturing is easier, but gate electrode height uniformity deteriorates
Solution Approach 1:
The patent introduces a planarization layer as an intermediary that decouples the sacrificial layer height variations from the gate electrode height control. The planarization layer absorbs the variations in sacrificial layer height and provides a uniform surface for subsequent gate electrode formation. This intermediary structure allows the sacrificial layer to be formed easily with varying heights in different regions while maintaining uniform gate electrode heights, as the planarization layer masks the underlying variations.
Solution Approach 2:
The patent applies preliminary action by forming the planarization layer before gate electrode formation to pre-compensate for sacrificial layer height variations. This preliminary planarization step creates a flat reference surface that enables uniform gate electrode heights regardless of the sacrificial layer's underlying variations. The preliminary action of planarization separates the ease of sacrificial layer formation from the precision requirement of gate electrode height, allowing both objectives to be achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform gate electrode height and stable threshold voltages across semiconductor devices, improving manufacturing reliability and reducing variations caused by density differences in transistor areas.
Implementation Method 1
planarizing the sacrificial layer without exposing the insulation pattern to thereby form a sacrificial pattern in the gate trench
Implementation Method 2
etching portions of the work function metal layer and the gate dielectric layer to form respective gate dielectric patterns and work function metal patterns
Data Source
AI summary
Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.