Gate Trench Polysilicon Shielding for Oxide Field Reliability
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Solution Overview
Problem
Existing power semiconductor devices with gate trenches face challenges such as oxide reliability issues due to high electric fields at sharp corners, which can lead to device failure, and complex manufacturing processes.
Innovation Solution
The use of doped polysilicon layers as shielding material within the gate trenches to reduce electric field levels and simplify the manufacturing process, eliminating the need for deep trench shielding patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trench shielding patterns are used to reduce electric field effects, then oxide reliability is improved, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent changes the electrical parameters of the polysilicon layer by applying specific doping concentrations and depths. The polysilicon layer is doped to have a conductivity type opposite to the substrate (e.g., p-type in n-type substrate) with doping concentrations ranging from 1E18 to 1E20 atoms/cm³, creating an electrical shield that reduces peak electric fields at the gate oxide interface without requiring complex geometric trench structures
Solution Approach 2:
The polysilicon layer acts as an intermediary element between the metal gate and the semiconductor substrate. This intermediate layer modifies the electric field distribution by introducing a oppositely-doped region that counteracts the high field effects, thereby protecting the gate oxide without requiring direct geometric modifications to the trench structure
2Reliability
If deep trench shielding patterns are used to reduce electric field effects, then oxide reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The polysilicon layer is formed and doped before the gate oxide is deposited. This preliminary action establishes the electric field shielding configuration in advance, allowing subsequent gate oxide formation to proceed without additional complex steps. The doping is performed at a defined depth (e.g., 50-200 nm from the gate interface) to ensure optimal shielding效果 before oxide deposition
Solution Approach 2:
The patent uses standard semiconductor doping techniques with controllable parameters (doping concentration, depth, and distribution) to create the shielding effect. By adjusting doping parameters rather than geometric parameters, the process leverages existing manufacturing capabilities without requiring new complex fabrication steps
3Ease of manufacture
If polysilicon layers are used as shielding material, then manufacturing process is simplified, but electric field reduction effectiveness may be compromised
Solution Approach 1:
The patent optimizes the electrical parameters of the polysilicon layer including doping concentration (1E18 to 1E20 atoms/cm³), doping depth (50-200 nm from gate interface), and layer thickness to achieve effective electric field reduction. These parameter optimizations ensure that the simplified polysilicon-based approach maintains shielding effectiveness comparable to or exceeding traditional deep trench structures
Solution Approach 2:
The patent replaces the mechanical/geometric shielding approach (deep trench structures) with an electrical field-based shielding approach using doped polysilicon. Instead of relying on physical distance and geometric configuration to reduce electric fields, the invention uses controlled electrical properties (doping concentration and distribution) to achieve field reduction, thereby simplifying the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the gate oxide by reducing high electric field effects and simplifies the manufacturing process, leading to improved device performance and reduced production costs.
Implementation Method 1
The use of doped polysilicon layers as shielding material within the gate trenches to reduce electric field levels
Data Source
AI summary
Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.