Gate Trench Segmentation for Semiconductor Data Retention
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Solution Overview
Problem
The miniaturization of semiconductor devices increases resistance values, limiting integration, and the use of metal layers in gate patterns complicates re-oxidization processes, leading to data retention degradation and poor gap-fill characteristics of contact plugs due to high aspect ratios of contact holes.
Innovation Solution
A method of fabricating semiconductor devices where upper gate patterns including a metal layer are formed within gate trenches and contact plugs are created simultaneously, using tungsten for low-resistance wiring, allowing for a re-oxidization process without abnormal oxidation and reducing the aspect ratio of contact holes for improved gap-filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer is used in the gate pattern to reduce resistance, then the resistivity of conductive patterns is reduced, but the re-oxidization process becomes difficult to perform and data retention degradation occurs
Solution Approach 1:
The gate pattern is segmented into two parts: the lower gate pattern (polysilicon-based) that undergoes re-oxidization, and the upper gate pattern (metal-based) that provides low resistance. This segmentation allows each part to fulfill its specific function without compromising the other.
Solution Approach 2:
The gate structure transitions from a two-dimensional planar structure to a three-dimensional stacked structure with lower and upper gate patterns at different vertical levels. This dimensional change enables the coexistence of polysilicon and metal layers with distinct functional roles.
2Manufacturing precision
If the aspect ratio of contact holes is reduced to improve gap-fill characteristics, then the gap-fill characteristic of contact plugs is improved, but the height of contact holes must be reduced which conflicts with the increased height due to metal layer
Solution Approach 1:
The contact hole formation process is segmented into two stages: first forming contact holes through the pre-metal dielectric layer to a first depth, then forming gate trenches deeper to expose the lower gate pattern. This segmentation allows contact holes to have optimized dimensions for gap-filling while gate trenches provide the necessary depth for metal layer formation.
Solution Approach 2:
Contact holes are formed preliminarily before forming the gate trenches. This preliminary action establishes the contact plug formation foundation with optimized aspect ratio, and subsequent gate trench formation does not interfere with the already-formed contact holes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents data retention degradation and enhances the gap-fill characteristics of contact plugs, ensuring stable semiconductor device performance by allowing for effective re-oxidization and reduced aspect ratios in contact holes.
Implementation Method 1
a re-oxidization process for removing the damaged portions must be performed so as to prevent degradation of data retention characteristics
Implementation Method 2
a method of utilizing a metal layer of low resistivity, such as tungsten (W), as the conductive pattern has recently been introduced
Data Source
AI summary
A method of fabricating a semiconductor device, in which although a metal layer is included in a gate pattern, the gap-fill characteristic of contact plugs coupled to junctions can be improved and degradation in the data retention characteristic can also be prevented. According to the method, a semiconductor substrate in which lower gate patterns and gate hard mask patterns are sequentially stacked is first provided. Junctions are formed in the semiconductor substrate on both sides of each of the lower gate patterns. A first pre-metal dielectric layer is formed over the semiconductor substrate in which the hard mask patterns and the junctions are formed. Contact holes through which the junctions are exposed are formed in the first pre-metal dielectric layer. Gate trenches through which the lower gate patterns are exposed are formed by removing the hard mask patterns. Upper gate patterns, each including a metal layer, are formed in the gate trenches, and first contact plugs are formed in the contact holes.