Gate Trench Semiconductor Device Reducing Active Region
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Solution Overview
Problem
Conventional methods for manufacturing MOS transistors on semiconductor substrates require multiple mask patterns, leading to increased manufacturing costs and difficulties in reducing the active region size, which results in high aspect ratios and sub-threshold current issues due to the short-channel effect.
Innovation Solution
A semiconductor device and manufacturing method that involves forming a gate trench on the semiconductor substrate, burying a gate electrode within it, and using self-aligned contact plugs, eliminating the need for a separate mask pattern for contact formation and reducing the active region, thereby reducing the aspect ratio and sub-threshold current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If three mask patterns are used to form field-forming insulation film, gate electrode, and contact plug, then manufacturing precision is improved, but device complexity increases and manufacturing cost increases
Solution Approach 1:
The patent combines the formation of the contact plug and gate electrode into a single photolithography step by using a combined mask pattern that defines both structures simultaneously. This merging eliminates the need for separate mask patterns for contact plugs and gate electrodes, reducing the total number of photolithography steps from three to two while maintaining positional accuracy through self-alignment features.
Solution Approach 2:
The field-forming insulation film serves multiple functions: it acts as a mask for forming contact plugs, defines the active region boundaries, and provides electrical isolation. This multi-functionality reduces the need for additional dedicated mask patterns, thereby simplifying the overall manufacturing process while maintaining precision.
2Manufacturing precision
If margin is secured for contact plug formation, then manufacturing precision is improved, but area of active region increases
Solution Approach 1:
The contact plug position is determined by self-alignment to the gate electrode structure rather than requiring an independent margin-based mask pattern. The gate electrode sidewalls serve as natural alignment references, allowing the contact plug to be precisely positioned without adding extra margin to the active region area.
3Reliability
If cap insulation film is added on gate electrode, then reliability is improved, but aspect ratio increases
Solution Approach 1:
The patent extracts the cap insulation film from the top of the gate electrode and relocates it to the bottom of the gate trench, where it serves as a base insulation layer. This extraction eliminates the need for a thick cap insulation film on top, thereby reducing the total film thickness and aspect ratio while maintaining insulation reliability through the relocated insulation structure.
4Shape
If damascene process is used to reduce aspect ratio, then shape is improved, but manufacturing steps increase
Solution Approach 1:
The patent performs preliminary action by forming the gate electrode and contact plug structures in a specific sequence during the photolithography process, rather than using the damascene approach of filling trenches. This preliminary structuring allows for direct formation of low aspect ratio features without requiring additional filling and planarization steps, thereby reducing overall manufacturing complexity.
Data Source
AI summary
After an element isolation region is formed using a field-forming silicon nitride film, the silicon nitride film and a semiconductor substrate are patterned. Thereafter, the silicon nitride film and the semiconductor substrate are patterned, thereby forming a gate trench reaching the semiconductor substrate in an active region. Next, after a gate electrode is formed within a gate trench, the silicon nitride film is removed, thereby forming a contact hole. A contact plug is buried into this contact hole. Accordingly, a diffusion layer contact pattern becomes unnecessary, and the active region can be reduced. Because a gate electrode is buried in the gate trench, a gate length is increased, and a sub-threshold current can be reduced.