Gate Trench Shield Connections for Lower Oxide Corner Stress
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power semiconductor devices face challenges in maintaining reliability due to high electric field degradation of the gate insulating layer, particularly at the corners of gate trenches, leading to potential breakdown and reduced blocking capabilities.
Innovation Solution
The introduction of deep shielding patterns and conduction enhancing regions with varying dopant concentrations in the drift region, which shift the peak electric field distribution away from susceptible areas, reducing the electric field strength at corners and enhancing the device's blocking voltage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep shielding patterns are introduced to protect the gate insulating layer, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by introducing deep shielding patterns specifically at the corners of gate trenches where electric field concentration is highest. Rather than uniformly shielding the entire gate structure, the invention targets only the vulnerable corner regions with heavily doped semiconductor regions, providing localized protection where it is most needed while minimizing overall device complexity
Solution Approach 2:
The deep shielding patterns are formed during the epitaxial growth process before final device assembly. By pre-forming these protective structures in the drift region during initial fabrication steps, the patent eliminates the need for additional complex shielding layers or structures to be added later, thereby improving reliability without proportionally increasing device complexity
2Strength
If conduction enhancing regions with higher dopant concentration are added, then blocking voltage capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes by varying the dopant concentration in specific regions of the drift layer. Conduction enhancing regions are formed with higher dopant concentrations (e.g., 1E16 to 1E18 atoms/cm³) compared to the lightly doped drift region (e.g., 1E14 to 1E16 atoms/cm³). This controlled variation in doping parameters enables enhanced blocking voltage capability while managing manufacturing precision through established semiconductor fabrication techniques
Solution Approach 2:
The invention applies local quality by creating regions with different dopant concentrations in specific locations. Conduction enhancing regions are positioned adjacent to gate trenches where they provide localized electric field management, while the bulk drift region maintains lower doping for high voltage blocking. This spatial variation in material properties achieves enhanced performance without requiring uniform high-precision doping throughout the entire device
3Reliability
If the drift region is lightly doped to reduce electric field strength, then gate oxide breakdown is prevented, but device resistance increases
Solution Approach 1:
The patent applies segmentation by dividing the drift region into functionally distinct zones: lightly doped regions for voltage blocking and high-voltage stress areas, and heavily doped conduction enhancing regions for current flow paths. This segmentation allows the device to simultaneously achieve low electric field strength in critical areas (protecting gate oxide) while maintaining low overall resistance through parallel conduction paths in the enhanced regions
Solution Approach 2:
The invention uses local quality by creating spatial variations in dopant concentration within the drift region. Lightly doped areas (1E14-1E16 atoms/cm³) are positioned where high electric field management is needed to protect the gate insulating layer, while locally concentrated heavily doped regions (1E16-1E18 atoms/cm³) are placed in conduction enhancing positions to provide low-resistance current paths, thus resolving the contradiction between oxide protection and resistance reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the reliability and performance of power semiconductor devices by reducing the likelihood of gate oxide breakdown and maintaining or improving device performance while compensating for increased resistance in lightly doped regions.
Implementation Method 1
shift the peak electric field distribution away from susceptible areas, reducing the electric field strength at corners
Implementation Method 2
respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration
Data Source
AI summary
A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region. The drift region comprises a first concentration of dopants of the first conductivity type, and the respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration. Related devices and fabrication methods are also discussed.