Self-Aligned Gate Trench Shielding for Power MOSFET Oxide Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power MOSFETs with gate trenches are prone to oxide reliability issues due to high electric fields, leading to premature breakdown of the gate oxide layer, which can result in device failure, and conventional trench shielding techniques face challenges in alignment and doping concentration optimization.
Innovation Solution
The implementation of self-aligned trench shielding regions formed using a multi-level mask structure during ion implantation and etching processes, allowing for optimized width control and alignment with gate trenches, reduces electric field levels and enhances device performance by minimizing unintended dopant implantation into sidewalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional trench shielding techniques are used, then alignment and doping concentration optimization are achieved, but oxide reliability issues occur due to high electric fields leading to premature breakdown
Solution Approach 1:
A p-type shielding region is introduced as an intermediary structure between the gate trench and the n- drift region. This shielding region acts as a mediator to reduce the electric field concentration at the gate oxide interface, thereby preventing premature breakdown while maintaining proper alignment through self-aligned fabrication techniques
Solution Approach 2:
The invention modifies the doping parameters by creating a p-type shielding region with specific doping concentrations (1×10^16 to 1×10^18 atoms/cm³) and dimensions (width greater than gate trench width, depth of 0.5-2.0 micrometers). These parameter changes optimize the electric field distribution to protect the gate oxide layer
2Manufacturing precision
If gate trenches are implemented, then device structure is improved, but alignment challenges and unintended dopant implantation into sidewalls occur
Solution Approach 1:
The fabrication process utilizes self-aligned techniques where the p-type shielding region is formed in direct alignment with the gate trench through a single ion implantation step. The gate trench structure itself serves as the alignment reference, eliminating the need for separate alignment steps and preventing unintended dopant implantation into sidewalls
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively extends the lifespan of the gate oxide layer, improves device voltage rating, and optimizes performance for various applications by controlling specific on-resistance and electric field values, thereby enhancing the reliability and efficiency of power MOSFETs.
Implementation Method 1
reduces electric field levels and enhances device performance by minimizing unintended dopant implantation into sidewalls
Implementation Method 2
Dopants are implanted into the semiconductor layer structure through the second opening to form an implanted region in the semiconductor layer structure
Data Source
AI summary
A method of forming a semiconductor device comprises forming a first mask that includes a longitudinally-extending first opening that has a first width on a semiconductor layer structure. A spacer is formed on sidewalls of the first mask that are exposed by the first opening to form a second mask, where the first and second masks comprise a mask structure that has a longitudinally-extending second opening that has a second width that is smaller than the first width. Dopants are implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacer is at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure underneath the third opening.