Gate Trench Thick Bottom Oxide Formation
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Solution Overview
Problem
In power MOSFETs with stand-alone gate trenches, the increased parasitic gate-drain charge (Qgd) due to the overlap between the gate electrode and the silicon substrate results in reduced switching performance, and existing methods for forming a thick bottom oxide are challenging to implement, especially for small device features and high aspect ratios.
Innovation Solution
A dual protective layer structure is used, where a first dielectric layer protects the top corners of the trench and a second dielectric layer lines the sidewalls and bottom without an intervening oxide, allowing for independent thickness tuning and precise removal to form a thick bottom oxide, thereby reducing Qgd and maintaining trench integrity over a wide process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a thick bottom oxide is formed using HDP CVD or damage implant, then the parasitic gate-drain charge is reduced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The protective layer is segmented into two distinct layers: a first protective layer covering the top portion of the trench and a second protective layer covering the bottom portion. This segmentation allows independent thickness control and selective removal of each layer, enabling precise formation of thick bottom oxide while protecting sidewalls, thus reducing parasitic gate-drain charge without excessive manufacturing complexity
Solution Approach 2:
The patent applies different protective layer configurations at different locations within the trench. The bottom portion receives a thinner second protective layer that can be completely removed to enable thick oxide formation, while the top portion receives a thicker first protective layer that remains to protect against over-oxidation. This local differentiation achieves the desired oxide profile while managing process complexity
2Ease of manufacture
If a single protective layer is used to protect sidewalls and top during bottom oxidation, then the manufacturing process is simpler, but it is difficult to ensure complete removal at the bottom while protecting other parts, especially for small features and high aspect ratios
Solution Approach 1:
The protective layer is divided into a first protective layer for the top portion and a second protective layer for the bottom portion. The second layer is designed with specific thickness to enable complete removal at the trench bottom while the first layer remains to protect the top. This segmentation provides independent control over protection at different locations, achieving both manufacturing simplicity and removal precision
Solution Approach 2:
The solution moves from a single-layer protective approach to a multi-layer vertical structure. By stacking protective layers with different thicknesses and removal characteristics, the patent adds a dimensional aspect to protective layer design, enabling precise spatial control of oxidation while maintaining process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic gate-drain charge and ensures high gate trench structure integrity, improving switching performance across a wide range of device sizes and aspect ratios.
Implementation Method 1
removing the second dielectric layer from at least part of the bottom of the trench to expose part of the semiconductor substrate
Implementation Method 2
oxidizing the exposed part of the semiconductor substrate to form an oxide region at the bottom of the trench
Implementation Method 3
lining the sidewalls and bottom of the trench with a second dielectric layer without an intervening oxide layer along the sidewalls and bottom of the trench
Data Source
AI summary
An insulated gate trench is manufactured by forming a first dielectric layer on a semiconductor substrate, forming a hardmask on the first dielectric layer and etching a trench into the semiconductor substrate through an opening in the hardmask and the first dielectric layer, the trench having sidewalls and a bottom. The sidewalls and bottom of the trench are lined with a second dielectric layer without an intervening oxide layer along the sidewalls and bottom of the trench. The second dielectric layer is removed from at least part of the bottom of the trench to expose part of the semiconductor substrate, and the exposed part of the semiconductor substrate is removed to form an oxide region at the bottom of the trench. Subsequently, a gate dielectric is formed on the sidewalls and bottom of the trench and a gate electrode in the trench without a separate field electrode in the trench.