Gate Trench Transistor Insulating Metal Layer Leakage Reduction
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Solution Overview
Problem
The increasing integration density of semiconductor devices leads to electrical property deterioration due to leakage currents in source/drain regions, particularly in 3-dimensional transistors, which affects their switching characteristics.
Innovation Solution
A semiconductor device design featuring a gate structure with a gate electrode, insulating gate capping pattern, and an insulating metal-containing material layer within a gate trench, where the metal layer has a Fermi energy closer to the conduction or valence band of the energy band diagram, reducing leakage currents by inhibiting charge loss in source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of semiconductor devices is increased, then device miniaturization and higher capacity are achieved, but leakage currents in source/drain regions increase causing deterioration in electrical properties
Solution Approach 1:
An insulating metal-containing material layer is introduced as an intermediary between the gate structure and the source/drain regions. This layer acts as a mediator to suppress leakage currents by modifying the energy band alignment, creating a barrier that prevents charge carrier tunneling while allowing the device to maintain high integration density
Solution Approach 2:
The invention changes the energy band parameters by selecting metals with specific work functions (Fermi energy levels) for the insulating metal-containing material layer. By adjusting the Fermi energy to be closer to the conduction or valence band edge, the device optimizes the energy barrier height to suppress leakage currents while maintaining acceptable on-current characteristics
2Speed
If 3-dimensional transistor structure is used, then switching speed and integration density are improved, but leakage currents increase leading to charge loss in source/drain regions
Solution Approach 1:
The insulating metal-containing material layer serves as an intermediary that suppresses gate-induced drain leakage (GIDL) by modifying the electric field distribution and energy band structure in the drain region, thereby reducing charge loss while preserving the fast switching characteristics of 3-dimensional transistors
Solution Approach 2:
The insulating metal-containing material layer is selectively applied in specific regions (between the gate electrode and source/drain regions) rather than uniformly across the entire device. This local modification targets the leakage current paths without affecting the overall switching performance of the transistor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage currents and maintains charge storage in source/drain regions, enhancing the electrical properties and switching characteristics of 3-dimensional transistors.
Implementation Method 1
the insulating metal-containing material layer may include a metal that may have a Fermi energy closer to a conduction band of an energy band diagram of the active region than to a valance band of the energy band diagram of the active region
Data Source
AI summary
A semiconductor device including a buried cell array transistor and an electronic device including the same are provided. The device includes a field region in a substrate and the filed region defines an active region. A first source/drain region and a second source/drain region are in the active region. A gate trench is between the first and second source/drain regions, and in the active region and the field region. A gate structure is within the gate trench. The gate structure includes a gate electrode, an insulating gate capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an insulating metal-containing material layer between the insulating gate capping pattern and the active region.