Semiconductor Gate Trench Wiring Layout for Lower Inductance
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Solution Overview
Problem
Current semiconductor devices face challenges in optimizing electrical performance due to limitations in trench structure configurations and doping concentrations, which affect the device's ability to manage electric field strength and reduce parasitic inductance.
Innovation Solution
The semiconductor device incorporates a specific trench structure configuration with alternating gate trench and dummy trench portions, along with a trench bottom region and well region, to enhance electric field management and reduce resistance, thereby improving the device's electrical performance and withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional trench structure configurations are used, then manufacturing is simpler, but electrical performance and parasitic inductance management are insufficient
Solution Approach 1:
The gate wiring is divided into multiple segments by introducing dummy trench portions between adjacent gate trench portions. This segmentation reduces parasitic inductance by breaking up current paths and distributing electromagnetic interference, thereby improving electrical performance while managing complexity through systematic division of the gate structure.
Solution Approach 2:
Dummy trench portions are strategically positioned at specific locations between gate trenches where parasitic inductance and electric field concentration are most problematic. This localized modification optimizes electrical performance at critical points without requiring complete restructuring of the entire device, balancing improvement with manufacturing feasibility.
2Reliability
If doping concentration is increased to reduce resistance, then electrical performance improves, but control over electric field strength becomes more difficult
Solution Approach 1:
Dummy trench portions act as intermediary structures between gate trenches, providing regions with controlled doping concentrations that mediate between the high doping needed for low resistance and the electric field management requirements. These intermediary regions distribute electric field stress and enable resistance reduction without compromising electric field control.
Solution Approach 2:
The doping concentration is varied spatially across different regions of the trench structure. Higher doping concentrations are applied in regions where resistance reduction is prioritized, while lower doping concentrations are maintained in regions where electric field strength control is critical. This parameter optimization allows simultaneous improvement of both electrical performance and electric field management.
3Reliability
If trench depth is increased to improve withstand voltage, then electrical performance improves, but parasitic inductance and manufacturing difficulty increase
Solution Approach 1:
The deep trench structure is segmented into multiple sections with alternating gate trenches and dummy trenches. This segmentation allows the total trench depth to be achieved while distributing manufacturing complexity across multiple shallower etching steps and enabling better control over trench profile and doping uniformity, thus improving manufacturability without sacrificing withstand voltage capability.
Data Source
AI summary
A semiconductor device including an active portion is provided, the semiconductor device comprising: a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; a gate pad provided above the semiconductor substrate; an emitter electrode provided above the semiconductor substrate; a gate trench portion provided on a front surface of the semiconductor substrate in the active portion; and a gate wiring portion for connecting the gate pad and the gate trench portion; wherein the gate wiring portion has: a first gate trench wiring portion which extends in a predetermined direction; and a second gate trench wiring portion which extends in a different direction from the first gate trench wiring portion and intersects the first gate trench wiring portion at an intersection portion; and the emitter electrode is provided above the intersection portion.