Reconfigurable Gate-Tunneling PUF Cell for Stable CMOS Outputs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing PUFs based on CMOS devices suffer from instability due to noise and require additional silicon area for error correction, leading to increased complexity and latency in determining stable output bits.
Innovation Solution
A reconfigurable PUF cell design splits CMOS devices into multiple sub-devices, allowing for reconfiguration to maximize the difference in output currents, reducing instability and silicon area requirements through a differential pulse-width modulation analog front-end and time-to-digital converter system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PUF cells are designed using traditional CMOS devices, then the circuit is simple, but the output stability is poor due to noise
Solution Approach 1:
Each PUF cell is divided into multiple sub-cells, where each sub-cell contains two CMOS devices. The switching devices can selectively connect these sub-cells to different outputs, allowing the cell to be reconfigured into different configurations. This segmentation enables the system to overcome noise-induced instability by providing multiple possible output states from which a stable one can be selected.
Solution Approach 2:
The PUF cell incorporates switching devices that enable dynamic reconfiguration of the CMOS devices between different outputs. This dynamic capability allows the cell to adapt its configuration in response to noise or instability conditions, selecting the configuration that produces the most stable output. The system can switch between configurations to maintain reliable operation despite environmental variations.
2Reliability
If reconfigurable PUF cells are implemented to improve stability, then output stability increases, but the silicon area increases
Solution Approach 1:
By dividing each PUF cell into multiple smaller sub-cells with shared switching devices, the design achieves reconfigurability without proportionally increasing total silicon area. The sharing of switching devices and the compact arrangement of sub-cells allow the cell to provide multiple configurations within a constrained area, reducing the area overhead compared to implementing separate dedicated cells for each configuration.
Solution Approach 2:
The switching devices and CMOS sub-cells are designed to serve multiple functions: they can be configured to produce different output combinations, enabling a single physical cell to replace what would otherwise require multiple separate cells. This multi-functionality increases output stability through reconfigurability while minimizing the additional silicon area required.
3Reliability
If error correction mechanisms are added to handle unstable outputs, then reliability improves, but device complexity and latency increase
Solution Approach 1:
The system performs preliminary action by proactively providing multiple pre-configured output states through the reconfigurable cell design. Instead of detecting errors and then correcting them (which would require complex error correction mechanisms), the system pre-establishes multiple valid configurations, allowing it to directly select a stable output without needing separate error detection and correction circuits. This reduces both complexity and latency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reconfigurable PUF cell design significantly reduces the probability of unstable outputs, minimizing the need for error correction and silicon area, while reducing latency in determining stable configurations.
Implementation Method 1
a first gate-tunneling current is generated by a first CMOS device at a left cell output and a second gate-tunneling current is generated by a second CMOS device at a right cell output
Data Source
AI summary
There is provided a circuit for a physical unclonable function comprising: first and second outputs; a cell comprising a plurality of CMOS devices; and a plurality of switching devices, the plurality of switching devices operable to connect a gate terminal of each of the plurality of CMOS devices to one of the first and second outputs, wherein a quantity of the plurality CMOS devices is a multiple of two, and wherein the circuit is configured such that each of the first and second output is connected to an equal quantity of the plurality of CMOS devices.