Gate Electrode Via Insulation Structure for Breakdown Reliability
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Solution Overview
Problem
The existing semiconductor devices face challenges in preventing defects during the pad structure formation process, particularly in securing electrical insulation between the through via and the gate electrodes, which affects the reliability and breakdown voltage of the device.
Innovation Solution
The semiconductor device incorporates a separation insulating layer with varying thicknesses formed using a selective deposition process, and a wet etching process is employed to ensure electrical insulation between the through via and the gate electrodes, preventing over-etching issues and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through via is formed to pass through gate electrodes to improve electrical connection, then electrical conductivity is improved, but electrical insulation between the through via and adjacent gate electrodes deteriorates
Solution Approach 1:
An insulating pattern is introduced as an intermediary element between the through via and the adjacent gate electrodes. This insulating pattern is formed on the sidewalls of the gate electrodes and extends into the via hole, providing a physical and electrical barrier that prevents direct contact and potential breakdown between the conductive via and the gate electrodes, thus maintaining electrical insulation while allowing the via to pass through.
Solution Approach 2:
The insulating pattern is applied locally and selectively in the regions where electrical insulation is critical - specifically on the sidewalls of gate electrodes adjacent to the through via. This localized application ensures insulation where needed without interfering with the overall electrical connection function of the via structure.
2Manufacturing precision
If wet etching is used to form the via hole to improve manufacturing precision, then via hole shape control is improved, but over-etching occurs causing reliability deterioration
Solution Approach 1:
The insulating pattern is formed on the gate electrode sidewalls before the via hole is completely formed. This preliminary action creates a protective layer that prevents the etching process from directly exposing the gate electrode to the via filling material, thereby preventing over-etching damage and reliability deterioration while still allowing precise via hole formation.
Solution Approach 2:
The insulating pattern serves as a cushioning layer that absorbs or mitigates the harmful effects of the wet etching process. By being present beforehand on the gate electrode sidewalls, it prevents direct etching damage to the gate electrode structure during via hole formation, thus cushioning against reliability deterioration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively limits reliability deterioration due to over-etching and secures sufficient electrical insulation, thereby improving the structural stability and performance of the semiconductor device.
Implementation Method 1
a separation insulating layer with varying thicknesses formed using a selective deposition process
Implementation Method 2
a wet etching process is employed to ensure electrical insulation between the through via and the gate electrodes
Data Source
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AI summary
A semiconductor device may include gate electrodes spaced apart from each other in a first direction on a substrate and including pads in a stepped shape, a channel extending through the gate electrodes, a first through via, first and second separation insulating layers, and an insulating pattern. The gate electrodes may include second gate electrodes below a first gate electrode. The first through via may pass through and electrically connect to a first pad of the first gate electrode, pass through the second gate electrodes, and include a connection portion connected to a conductive pillar. The connection portion may contact the first pad. The first separation insulating layer may be on an upper surface of the connection portion. The second separation insulating layer may be on a bottom surface of the connection portion. The insulating pattern may be between the first through via and sidewalls of the second gate electrodes.