Gate Via Seed Layer Sequencing to Prevent Leakage and Seams

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Solution Overview

Problem

The epitaxial growth of a seed layer during the formation of a gate via in semiconductor structures can lead to current leakage and electrical shorts, reducing efficiency and breakdown voltage, and increasing the likelihood of seam formation.

Innovation Solution

Depositing a seed layer after the formation of the neighboring drain contact using conformal chemical vapor deposition (CVD) and conformal dry etching, with materials like ruthenium (Ru), molybdenum (Mo), or tungsten (W), to prevent lateral growth and reduce seam formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a seed layer is deposited before forming the drain contact, then the gate via can be formed, but epitaxial growth causes current leakage and electrical shorts

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidcurrent leakage and electrical shorts
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by forming the drain contact (metal interconnect layer) before depositing the seed layer. This sequence prevents the seed layer from growing laterally onto the drain contact, eliminating the harmful current leakage path while still allowing the seed layer to provide its intended function for gate via formation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the formation process into distinct sequential steps: first forming the drain contact, then depositing the seed layer, and finally forming the gate via. This segmentation isolates the seed layer deposition to specific regions, preventing unwanted epitaxial growth onto adjacent structures and eliminating electrical shorts.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If seed layer is deposited early, then gate via formation is enabled, but seam formation increases

Engineering Contradiction:
Improvegate via formationVSAvoidseam formation in gate via
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

By performing the drain contact formation as a preliminary action before seed layer deposition, the patent creates a controlled sequence that prevents seed layer material from contaminating adjacent regions. This preliminary structuring enables clean gate via formation without seams, maintaining both ease of manufacture and high precision.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances device performance, increases breakdown voltage, and reduces current leakage, thereby improving yield and conserving resources by minimizing electrical shorts and seam formation.

Implementation Method 1

Depositing a seed layer after the formation of the neighboring drain contact using conformal chemical vapor deposition (CVD)

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 2

conformal dry etching

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS20230395429A1Conductive structures and methods of forming the same
Publication Date: 2023.12.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230395429A1 patent drawing
  • US20230395429A1 patent drawing
  • US20230395429A1 patent drawing

AI summary

Depositing a seed layer after formation of the MD in order to reduce or prevent epitaxial growth of the seed layer toward the MD. For example, the seed layer may be deposited using CVD and conformal dry etching. In some implementations, the seed layer may be formed of ruthenium (Ru), molybdenum (Mo), or tungsten (W). Accordingly, the seed layer helps reduce or prevent seam formation in the VG, which reduces resistance of the VG by allowing for bottom-up metal growth. Additionally, current leakage from the VG to the MD is reduced or even prevented. As a result, device performance and efficiency are increased and breakdown voltage of the gate structure is also increased. Additionally, because electrical shorts are less likely, yield is increased, which conserves power, raw materials, and processing resources that otherwise would have been consumed during manufacture.