Gate Voltage Hold Control for Low-Surge Semiconductor Turn-Off
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Solution Overview
Problem
Existing semiconductor switching elements experience high surge voltages and ringing during turn-off, leading to increased electromagnetic noise and insulation issues.
Innovation Solution
A gate drive device with a gate voltage hold circuit that maintains a gate voltage at a predetermined hold voltage higher than the threshold but lower than the Miller voltage after detecting the rise in main terminal voltage during turn-off, reducing surge voltage and ringing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If gate driving speed is increased to reduce switching time, then switching losses decrease, but surge voltage increases
Solution Approach 1:
The gate voltage hold circuit is activated in advance during the voltage rise period (after voltage rise detection and before maximum voltage is reached) to preliminarily prepare the gate voltage at a hold level between threshold and Miller voltage. This preliminary action prevents the gate voltage from reaching Miller voltage during turn-off, thereby suppressing surge voltage while maintaining fast switching performance.
Solution Approach 2:
The gate voltage hold circuit dynamically adjusts the gate voltage during the switching transition by detecting the voltage rise and actively holding the gate voltage at a controlled level. This dynamic control allows the system to maintain fast switching (low loss) while preventing excessive surge voltage through real-time gate voltage modulation.
2Loss of energy
If gate driving speed is increased to reduce switching time, then switching losses decrease, but ringing occurs
Solution Approach 1:
The gate voltage hold circuit is activated in advance during the voltage rise period to preliminarily stabilize the gate voltage at a hold level. This preliminary stabilization prevents excessive voltage oscillations and ringing by controlling the gate voltage before the switching transition completes, while still allowing fast switching for low losses.
Solution Approach 2:
The gate voltage hold circuit provides dynamic stabilization during switching by detecting voltage rise and actively maintaining gate voltage within a controlled range. This dynamic control suppresses ringing oscillations while preserving fast switching performance for minimal energy loss.
3Object-affected harmful factors
If surge voltage is reduced by controlling gate voltage, then electromagnetic noise decreases, but switching performance may be affected
Solution Approach 1:
The gate voltage hold circuit is activated in advance during the voltage rise period to preliminarily set the gate voltage at an optimal hold level. This preliminary action reduces electromagnetic noise by preventing surge voltage while maintaining switching performance through controlled gate voltage during the critical transition period.
Solution Approach 2:
The gate voltage hold circuit dynamically controls gate voltage during switching transitions, optimizing the balance between electromagnetic noise reduction and switching performance. By actively adjusting gate voltage in real-time based on detected voltage rise, the system achieves low noise while maintaining fast switching capability.
Data Source
AI summary
A drive device for a voltage-driven semiconductor switching element includes: a gate drive circuit configured to drive the semiconductor switching element; and a gate voltage hold circuit configured to hold a gate voltage applied to the semiconductor switching element at a predetermined hold voltage higher than a threshold voltage of the semiconductor switching element and lower than a Miller voltage of the semiconductor switching element. The gate voltage hold circuit starts an operation of holding the gate voltage at the hold voltage after a rise of a voltage between main terminals of the semiconductor switching element at a turn-off time of the semiconductor switching element and before a maximum value of the voltage between the main terminals.