Gate Voltage Output Unit for LCD Ripple Reduction
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Solution Overview
Problem
Liquid crystal display devices experience image quality degradation due to voltage ripples caused by variations in gate voltages during the charging period, leading to flicker and reduced image clarity.
Innovation Solution
A gate driver is implemented with a gate voltage output unit that outputs specific on-level and off-level gate voltages to the nth and (n+1)th gate lines, ensuring stable voltage levels by selectively turning on/off high-level and low-level transistors during charging periods, minimizing rippling effects and optimizing display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate voltage is varied during charging period to enable sequential gate lines, then display functionality is achieved, but voltage ripple causes image quality degradation and flicker
Solution Approach 1:
The gate driver outputs a stable first off-level gate voltage to the nth gate line before charging begins. This preliminary voltage stabilization prevents ripple-induced image quality degradation during the subsequent charging period when the gate voltage is varied to enable sequential gate lines.
2Measurement precision
If multiple gate voltage levels are outputted during charging periods, then gate line control precision is improved, but device complexity increases
Solution Approach 1:
The gate driver circuit performs multiple functions using a unified structure: it outputs both the first off-level gate voltage before charging and the second off-level gate voltage after charging, eliminating the need for separate circuits for each voltage level and simplifying the overall device while maintaining precise gate line control.
Data Source
AI summary
A display device includes nth and (n+1)th gate lines in a display panel, wherein a pixel electrode of a pixel corresponding to the (n+1)th gate line overlaps the nth gate line; and a gate driver including a gate voltage output unit that outputs an on-level gate voltage and first and second off-level gate voltages to the nth gate line, wherein the on-level gate voltage is outputted during a charging period of the nth gate line, and the second off-level gate voltage is outputted during a charging period of the (n+1)th gate line.