Gate Voltage Plateau Completion Circuit for DC/DC Converters
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Solution Overview
Problem
Existing DC/DC switching converters face inaccuracies in detecting the end of the Miller plateau in gate voltage, leading to subharmonic oscillations and electromagnetic interference due to incorrect timing of the fast driver turn-on signal, affecting stability and efficiency.
Innovation Solution
A gate voltage plateau completion circuit that compares the gate voltage of a power NFET to the input supply voltage plus its threshold voltage, triggering a second gate driver to charge at a faster rate once the plateau is completed, ensuring accurate detection and optimal charging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single gate driver charges the gate at a constant rate, then the circuit is simple, but the timing of fast driver turn-on is inaccurate causing subharmonic oscillations and electromagnetic interference
Solution Approach 1:
The gate driver function is segmented into two separate gate drivers: a first gate driver that charges the gate at a first rate during the Miller plateau phase, and a second gate driver that charges at a second (faster) rate after plateau completion. This segmentation allows each driver to be optimized for its specific phase, improving detection accuracy while managing complexity through functional division.
Solution Approach 2:
The comparator continuously monitors the gate voltage and prepares the control signal for switching between gate drivers in advance. By detecting the plateau end condition (when gate voltage reaches input voltage plus threshold voltage) before the actual switching occurs, the system ensures accurate timing without requiring complex real-time decision-making circuitry.
2Stability of the object's composition
If the fast driver turns on too early or too late, then circuit stability improves, but electromagnetic interference increases due to incorrect timing
Solution Approach 1:
The comparator provides continuous feedback by monitoring the gate voltage and comparing it against the threshold condition (input voltage plus power NFET threshold voltage). This feedback mechanism ensures the second gate driver is activated at the precise moment the Miller plateau ends, maintaining stability while minimizing electromagnetic interference through accurate timing.
Solution Approach 2:
The patent replaces complex timing-based mechanical switching mechanisms with an electronic voltage comparison system. The comparator electronically detects the plateau end condition by comparing voltages, substituting mechanical timing circuits with a more precise and controllable electronic sensing approach that reduces electromagnetic interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides more accurate determination of the gate voltage plateau end, enhancing stability and efficiency by minimizing electromagnetic interference and achieving the lowest on-resistance, thus improving the overall performance of DC/DC switching converters.
Implementation Method 1
comparing, at the gate voltage plateau completion circuit, a gate voltage of the high-side power NFET to the input supply voltage plus the threshold voltage of the high-side power NFET
Implementation Method 2
driving the high-side power NFET using a first gate driver circuit that charges a gate of the high-side power NFET at a first rate; turning on a second gate driver circuit that charges the gate of the high-side power NFET at a second rate that is faster than the first rate
Data Source
AI summary
A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.