Gate-Voltage Tracking Circuit for High-Voltage Semiconductor Output
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Solution Overview
Problem
Existing semiconductor devices face a trade-off between suppressing hot carrier deterioration and maintaining high operation speed when generating output voltages with amplitudes higher than the transistor's withstand voltage, particularly in advanced processes.
Innovation Solution
A semiconductor device configuration using series-connected P-type and N-type transistors with a gate voltage control circuit that adjusts gate voltages to maintain transistor on-states during voltage changes, thereby suppressing hot carrier deterioration without reducing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate voltage is kept low to suppress hot carrier deterioration, then transistor reliability is improved, but operation speed decreases
Solution Approach 1:
The gate voltage control circuit dynamically adjusts the gate voltage of the first transistor based on the output voltage level. When the output voltage is high, the gate voltage is reduced to suppress hot carrier deterioration. When the output voltage is low, the gate voltage is increased to maintain high operation speed. This dynamic adjustment resolves the contradiction between reliability and speed.
Solution Approach 2:
The invention changes the gate voltage parameter conditionally based on the output voltage state. By controlling the gate voltage control circuit to output different voltage levels according to the output terminal voltage, the system optimizes the balance between suppressing hot carrier effects and maintaining fast switching speed.
2Adaptability or versatility
If transistors are used with withstand voltage matching low-amplitude input signals, then device compatibility is improved, but output voltage amplitude is limited
Solution Approach 1:
The gate voltage control circuit acts as an intermediary that enables the first transistor (with low withstand voltage) to safely operate in a high-voltage output environment. By dynamically controlling the gate voltage based on output conditions, it allows the transistor to generate high-amplitude output signals while preventing excessive voltage stress that would exceed its withstand capability.
Data Source
AI summary
A first P-type transistor and a second P-type transistor are connected in series between a power supply terminal and an output terminal. A first N-type transistor and a second N-type transistor are connected between a ground terminal and a power supply terminal. The second N-type transistor and the second P-type transistor are complementarily turned on and off in accordance with an input signal. A gate voltage control circuit changes at least one of the gate voltage of the P-type transistor whose drain is electrically connected to the output terminal and the gate voltage of the N-type transistor by following the output voltage VOUT of the output terminal while keeping the P-type transistor or the N-type transistor on-states.