Gate Redistribution Wire Bonds for Uniform Multi-Chip Switching
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Solution Overview
Problem
Conventional power device packages with ceramic-based carriers are expensive and have design limitations, such as high costs and non-uniform switch-on times due to varying wire bond connection characteristics, which affect the efficiency and cost-effectiveness of power transistor chip connectivity.
Innovation Solution
A power device package design featuring two power transistor chips with distinct wire bond connections, where the first wire bond connection is longer and has a greater cross-sectional area than the second, ensuring improved transient switch-on behavior and reduced manufacturing costs by using cheaper components connected in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ceramic-based carriers are used for mounting power transistor chips, then insulation performance and design flexibility are improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent uses a leadframe carrier that copies the essential functions of ceramic carriers (mechanical support, electrical connection, heat dissipation) while using cheaper materials and simpler manufacturing processes. The leadframe replicates the carrier functionality without requiring expensive ceramic substrates and complex trace patterning.
Solution Approach 2:
The patent employs a cost-effective leadframe carrier instead of expensive ceramic carriers, accepting that the carrier may have limited reusability or durability. This approach prioritizes low manufacturing cost over long-term carrier longevity, using disposable or single-use carriers to reduce overall system cost.
2Adaptability or versatility
If wire bond connections of different lengths are used to connect control electrodes, then design flexibility is improved, but switch-on time uniformity deteriorates
Solution Approach 1:
The patent applies different wire bond lengths and cross-sectional areas to different control electrode connections based on their specific requirements. Each wire bond is locally optimized for its particular function and position, allowing design flexibility while compensating for variations in switch-on timing through localized parameter adjustments.
Solution Approach 2:
The patent changes physical parameters of the wire bonds (length, cross-sectional area) to achieve desired electrical characteristics. By varying these parameters, the patent compensates for differences in connection paths and achieves more uniform switch-on times across parallel power transistor chips despite different wire bond geometries.
3Ease of manufacture
If parallel power transistor chips are connected with varying wire bond characteristics, then cost is reduced, but switching efficiency deteriorates
Solution Approach 1:
The patent systematically varies wire bond parameters (length, cross-sectional area, material) to optimize the electrical characteristics of each connection. This allows the use of simpler, cheaper parallel chip configurations while compensating for connection variations through parameter optimization, thereby maintaining switching efficiency despite cost-driven design choices.
Solution Approach 2:
The patent incorporates feedback mechanisms to monitor and adjust for variations in wire bond characteristics. By measuring actual connection properties and adjusting operating parameters or compensation circuits, the patent maintains consistent switching performance across parallel chips even when wire bond characteristics vary due to manufacturing tolerances or design differences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the switch-on behavior and reduces costs by using cheaper power transistor chips connected in parallel, achieving similar inductive switching delays and improving the efficiency of power device packages.
Implementation Method 1
A control package terminal is electrically coupled to the control electrode of the first power transistor chip via a first wire bond connection and to the control electrode of the second power transistor chip via a second wire bond connection
Implementation Method 2
achieving similar inductive switching delays
Data Source
Figure 1~2
Figure 3~4
Figure 5~7
AI summary
A power device package includes a first power transistor chip (120) having a control electrode (122), a first load electrode (124) and a second load electrode (126). The power device package further comprises a second power transistor chip (140) having a control electrode (142), a first load electrode and a second load electrode (146). A control package terminal (162) is electrically coupled to the control electrode (122) of the first power transistor chip (120) via a first wire bond connection (128) and to the control electrode (142) of the second power transistor chip (140) via a second wire bond connection (148). A first package terminal (164) is electrically coupled to the first load electrodes (124) of the first power transistor chip (120) and the second power transistor chip (140). A second package terminal (166) is electrically coupled to one or more of the second load electrodes (126, 146) of the first power transistor chip (120) and/or the second power transistor chip (140). A length of the first wire bond connection (128) is greater than a length of the second wire bond connection (148), and a cross-sectional area of the first wire bond connection (128) is greater than a cross-sectional area of the second wire bond connection (148).