Gate Workfunction Engineering for CMOS Short Channel Effects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CMOS devices face challenges in scaling physical channel length, leading to short channel effects such as reverse short channel effects, where halo doping regions overlap, increasing channel dopant concentration and threshold voltage, especially in shorter channel lengths.
Innovation Solution
The use of a workfunction setting material in gate stacks, proportionally modulated by channel length, to form conformal gate dielectric and metal layers, which helps in reducing short channel effects by adjusting the threshold voltage and dopant concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If halo doping is used to reduce depletion regions in short channel devices, then depletion region control is improved, but reverse short channel effect occurs where halo doping regions overlap and increase threshold voltage
Solution Approach 1:
The patent changes the workfunction parameter of the gate material to compensate for the reverse short channel effect. By selecting gate materials with appropriate workfunctions (e.g., tungsten for NFET, platinum for PFET), the threshold voltage is adjusted to counterbalance the unwanted voltage increase from halo doping overlap, thereby maintaining proper device characteristics despite the harmful effect.
2Productivity
If physical channel length is scaled down, then device density is improved, but short channel effects are exacerbated
Solution Approach 1:
The patent employs workfunction engineering as a parameter change strategy to mitigate short channel effects in scaled devices. By adjusting the gate material workfunction, the electrical characteristics of shortened channels are compensated, allowing higher device density while maintaining reliability through proper threshold voltage control.
Solution Approach 2:
The patent applies different workfunction settings to different device regions (NFET vs PFET) and adjusts the gate material composition locally to address specific short channel effects in each region, enabling tailored compensation for the varying short channel effects across the device array.
Data Source
AI summary
Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.