Non-Planar Gate Workfunction Split for I/O and Logic Transistors
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Solution Overview
Problem
The scaling of multi-gate transistors in semiconductor devices poses challenges due to constraints on semiconductor processes, particularly in achieving different workfunctions for I/O and logic transistors on common substrates without additional mask operations, which affects performance optimization.
Innovation Solution
The approach involves using a carbon hardmask to differentiate etch rates between different transistor structures, allowing for the patterning of distinct workfunction metal layers for I/O and logic transistors, enabling independent control of their performance without additional mask operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional multi-gate transistor fabrication processes are used on common substrates, then manufacturing simplicity is maintained, but different workfunctions for I/O and logic transistors cannot be achieved
Solution Approach 1:
The patent applies local quality by forming different workfunction metal layers in specific local regions corresponding to I/O transistor gate electrodes versus logic transistor gate electrodes. The process selectively deposits first and second workfunction metal layers in different areas of the substrate, enabling each transistor type to have its gate electrode with a tailored workfunction optimized for its specific performance requirements while using a single unified fabrication process flow.
2Adaptability or versatility
If additional mask operations are performed to achieve different workfunctions, then workfunction differentiation is enabled, but manufacturing complexity and process steps increase
Solution Approach 1:
The patent merges multiple functions into a single fabrication process sequence. By incorporating selective workfunction metal layer formation within the existing multi-gate transistor fabrication flow, the process simultaneously achieves gate electrode formation, workfunction differentiation, and device optimization without requiring separate mask operations or additional process modules. The first and second workfunction metal layers are deposited and patterned as integral parts of the gate electrode fabrication sequence.
Solution Approach 2:
The fabrication process exhibits universality by using a single process flow that can produce both I/O transistors and logic transistors with their respective workfunction requirements. The same fabrication sequence, including workfunction metal layer deposition and patterning steps, serves multiple purposes: forming gate electrodes, differentiating workfunctions for different device types, and optimizing performance characteristics all within one unified process framework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the independent targeting of performance for each device type, enhancing the efficiency of semiconductor device fabrication by enabling different actual gate workfunctions for I/O and logic transistors on a common substrate.
Implementation Method 1
The approach involves using a carbon hardmask to differentiate etch rates between different transistor structures, allowing for the patterning of distinct workfunction metal layers for I/O and logic transistors
Data Source
AI summary
Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.