Gate-Wrap-Around FET Fabrication Using Sacrificial Nanowire Spacers
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Solution Overview
Problem
Current processes for fabricating gate-wrap-around field-effect transistors face challenges in achieving controlled strain in channel zones, leading to performance dispersion due to poorly defined and controlled internal spacer positioning and width, which affects the desired strain in pMOS and nMOS transistors.
Innovation Solution
A process that forms internal spacers along a segment of nanowires extending from the source to the drain, preserving the channel zone and achieving high prestrain, involves ion implantation to amorphize SiGe nanowires, selective etching to create voids, and partial dielectric filling to form low-dielectric constant spacers, ensuring tensile strain in nMOS and compressive strain in pMOS channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If internal spacers are formed using conventional processes, then the transistor structure is created, but the positioning and width of internal spacers are poorly defined and controlled, leading to strain control issues in channel zones
Solution Approach 1:
A sacrificial nanowire is introduced as an intermediary element to define the position and width of internal spacers. The sacrificial nanowire serves as a template that is removed after spacer formation, leaving precisely controlled voids that are subsequently filled with dielectric material. This intermediary approach enables accurate spacer positioning and width control that cannot be achieved through direct formation methods.
Solution Approach 2:
The sacrificial nanowire is positioned and structured in advance before the internal spacers are formed. This preliminary action establishes the exact geometry and location where spacers will eventually reside, ensuring precise control over spacer dimensions and positioning. The sacrificial structure is prepared with the target spacer characteristics already encoded in its geometry.
2Ease of manufacture
If the channel zone is removed to form internal spacers, then spacers can be positioned, but the strain in channel zones is degraded
Solution Approach 1:
The sacrificial nanowire acts as a mediator that enables spacer formation without permanently removing the channel zone material. The channel zone is temporarily displaced or protected during spacer formation, then restored after the sacrificial nanowire is removed and voids are filled. This preserves the strain characteristics while enabling spacer placement.
Solution Approach 2:
The sacrificial nanowire is temporarily discarded to enable spacer formation, but the channel zone is recovered and restored after spacer placement. The sacrificial material is removed after serving its purpose as a template, and the channel zone structure is reestablished with its strain properties intact, now flanked by the newly formed internal spacers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of strain in channel zones, enhancing the electrical performance of transistors by maintaining tensile strain in nMOS and compressive strain in pMOS channels, thereby improving transistor performance and reducing power consumption.
Implementation Method 1
involves ion implantation to amorphize SiGe nanowires
Implementation Method 2
selective etching to create voids
Implementation Method 3
partial dielectric filling to form low-dielectric constant spacers
Implementation Method 4
In a step of growing silicon-germanium by epitaxy, a source and a drain are formed on either side of the stack
Data Source
AI summary
A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.