Gated-Clock Flip-Flop Circuit for Lower Switching Power
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Solution Overview
Problem
Conventional flip-flop elements in computer systems dissipate significant power due to clocking actions, even when the input data remains unchanged, leading to excessive power consumption.
Innovation Solution
A circuit element with a gated clock configuration that inverts and gates the clock signal based on the input data state, reducing unnecessary transitions and power consumption by controlling clock inversions according to the data state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clocking action is applied to all FET junctions on each clock cycle, then data capture functionality is achieved, but power dissipation increases significantly regardless of whether input data changes
Solution Approach 1:
The patent applies partial clocking action by selectively enabling clock signals only to latches that require updating. The gate control logic determines which latches receive clock signals based on input data changes, thereby avoiding unnecessary clocking action and reducing power dissipation while maintaining data capture functionality for only those latches that need to update their state
Solution Approach 2:
The patent implements local quality by applying different clocking behavior to different latches within the same flip-flop element. Each latch receives clock signals selectively based on its specific data capture needs, rather than applying uniform clocking to all latches. This localized approach reduces overall power consumption while maintaining necessary functionality
2Productivity
If clock signal is applied continuously to capture all data bits, then complete data capture is achieved, but unnecessary transitions occur when output state remains unchanged
Solution Approach 1:
The patent employs feedback mechanisms where the gate control logic monitors input data changes and uses this information to control clock signal distribution. The system feedbacks information about which latches need updating, enabling selective clocking that matches actual data capture requirements and avoids unnecessary transitions in latches whose output states remain unchanged
Solution Approach 2:
The patent implements dynamic clock signal distribution that adapts to changing data conditions. Rather than static continuous clocking, the system dynamically enables or disables clock signals to specific latches based on real-time detection of input data changes, optimizing the balance between data capture productivity and power consumption
3Reliability
If all FETs are configured in pairs to form inverters for robust switching, then circuit reliability is improved, but the number of FET transitions and power consumption increase
Solution Approach 1:
The patent extracts and removes the clock signal from parts of the circuit where it is not needed. By taking out the clock signal from latches that do not require updating, the system reduces the number of FET transitions in those sections while maintaining the robust inverter configuration only where necessary for reliable data capture
Data Source
AI summary
A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.