Gated-Clock Digital Noise Filter for Low-Power Signal Cleaning
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Solution Overview
Problem
Conventional digital noise filter circuits consume excessive power as they operate continuously regardless of noise presence or input signal changes, and increasing the noise removal width further escalates power consumption.
Innovation Solution
A digital noise filter circuit with a gating clock generating circuit that compares input and output signal logic levels, halting the clock when levels coincide, and a noise filter circuit using this gating clock for operation, reducing power consumption and enabling immediate filtering upon input signal changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the digital noise filter circuit operates continuously to remove noise, then noise removal effectiveness is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by controlling the clock signal to the noise filter circuit to operate only during necessary periods. The clock signal is enabled when the input signal changes state and disabled when the output signal stabilizes, transforming continuous operation into periodic operation that maintains noise removal effectiveness while reducing power consumption during stable periods
2Reliability
If the noise removal width is increased to filter more noise, then noise filtering capability is improved, but power consumption escalates
Solution Approach 1:
The patent applies dynamics by making the noise filter circuit's operation dynamic rather than static. The circuit adjusts its operational state based on real-time signal conditions, enabling the filter to process multiple noise cycles when needed while consuming minimal power when the signal is stable, thus improving noise filtering capability without proportional power consumption increase
3Use of energy by moving object
If the clock is halted to reduce power consumption, then power usage decreases, but signal changes may be missed
Solution Approach 1:
The patent applies feedback by using the output signal state to control the clock signal enabling/disabling. The circuit continuously monitors the output signal and adjusts the clock signal accordingly - enabling the clock when changes occur and disabling it when stable, ensuring signal changes are detected while minimizing power consumption during stable periods
Data Source
AI summary
A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal.