Clock Pulse Generation Circuit With Gated Set-Reset Timing
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Solution Overview
Problem
In clock pulse generation circuits, the simultaneous assertion of set and reset signals can lead to incorrect or inconsistent operation due to overlapping timing, which existing technologies fail to adequately address, especially in dense integrated circuits with varying timing constraints.
Innovation Solution
A clock pulse generation circuit is designed to prevent the set signal from being asserted when a reset signal is asserted, using a single pulse generator to generate the set signal based on the reset signal, thereby preventing override and ensuring consistent operation even when set and reset signals overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single pulse generator is used to generate both set and reset signals, then area and power consumption are reduced, but the risk of signal override and inconsistent operation increases when set and reset are asserted simultaneously
Solution Approach 1:
The patent applies preliminary action by generating the reset signal first and using it to control the timing of set signal generation. The reset signal is asserted before the set signal, and the set signal generation is conditioned on the reset signal state, ensuring that set cannot override reset even when both are needed simultaneously. This temporal ordering prevents the harmful overlap effect.
2Adaptability or versatility
If set and reset signals are generated independently, then signal timing flexibility is improved, but circuit complexity and verification time increase
Solution Approach 1:
The patent merges the set and reset signal generation functions into a single pulse generator circuit. Instead of having two independent pulse generators, the circuit uses one generator that produces reset signals and conditions set signal generation on the reset signal state. This consolidation reduces circuit complexity while maintaining the necessary timing flexibility through the conditional generation logic.
3Reliability
If set signal generation is conditioned on reset signal state, then signal override is prevented, but the generation logic becomes more complex
Solution Approach 1:
The patent uses an intermediary logic mechanism where the reset signal acts as a gate or condition for set signal generation. The set signal is generated based on the external clock signal and the state of the reset signal, creating a controlled dependency relationship. This intermediary conditioning prevents direct conflict between set and reset assertions while keeping the logic relatively simple through straightforward conditional generation.
Data Source
AI summary
In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.