Gated-Clock Sampling Check for Fault Injection Detection
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Solution Overview
Problem
Existing electronic devices are vulnerable to fault injection attacks, which can cause timing violations and unauthorized information leakage due to glitches or external interference, as current detection methods are inadequate in ensuring data-sampling integrity.
Innovation Solution
The implementation of a dual-sampling scheme using Flip-Flops (FFs) with a relative delay, where functional FFs and protection FFs sample outputs with a predefined time offset, allowing the detection of discrepancies and initiation of responsive actions to protect against signal instability and glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single sampling point is used to reduce circuit complexity, then device complexity is reduced, but reliability deteriorates due to vulnerability to fault injection attacks
Solution Approach 1:
The sampling process is segmented into multiple independent sampling operations performed at different time points. Instead of a single sampling point, the circuit performs first sampling at time T1 and second sampling at time T2, where each sampling operation is independent and can detect different types of faults that might affect only one specific time point.
Solution Approach 2:
The protection flip-flop performs a preliminary sampling operation at a different time point before the functional flip-flop samples. By sampling at time T2 (different from T1), the protection mechanism is already in place and can detect faults that occur during the functional sampling window, preventing erroneous data from being processed.
2Reliability
If multiple sampling points are used to improve detection capability, then reliability is improved, but device complexity increases
Solution Approach 1:
Multiple sampling operations are merged into a unified protection mechanism where the protection flip-flop and functional flip-flop share the same basic circuit structure. The XOR gate combines the results of multiple samplings to produce a single error detection signal, reducing the need for separate complex detection circuits for each sampling point.
Solution Approach 2:
The protection mechanism uses a copy of the functional circuit (protection flip-flop) that mirrors the structure of the functional flip-flop but operates at a different time point. This copying approach allows the same simple circuit design to be reused multiple times, maintaining low complexity while achieving reliable fault detection through temporal diversity.
3Measurement precision
If sampling occurs continuously to detect all faults, then measurement precision is improved, but loss of time increases due to additional sampling operations
Solution Approach 1:
Instead of continuous sampling, the protection mechanism uses periodic sampling at specifically chosen time points T1 and T2. These periodic sampling operations are synchronized with the clock signal and occur only when needed to detect potential faults, reducing time overhead while maintaining detection precision through strategic timing selection.
Solution Approach 2:
The sampling operation changes its temporal parameter by performing samples at different time offsets relative to the clock signal. The protection flip-flop is clocked with a delayed version of the clock signal, creating a time offset that allows detection of faults without requiring continuous monitoring, thus reducing time loss while maintaining precision.
Data Source
AI summary
An electronic device includes clock generation circuitry, a combinational logic circuit, one or more functional state-sampling components, and protection logic. The clock generation circuitry is configured to generate a clock signal having a periodic clock cycle. The combinational logic circuit includes multiple internal nets and one or more outputs. The functional state-sampling components are configured to sample the respective outputs of the combinational logic circuit periodically in accordance with the clock signal. The protection logic is configured to receive one or more signals from the internal nets or outputs of the combinational logic circuit, to detect, in one or more of the received signals, a signal instability that occurs during a predefined portion of the periodic clock cycle in which, in accordance with a design of the combinational logic circuit, the signals are expected to be stable, and to initiate a responsive action in response to the detected signal instability.