Type-Matched Gated Clock Tree for Low Clock Skew
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Solution Overview
Problem
Conventional clock tree design techniques fail to adequately control clock skew caused by different types of logic gates within the same level, leading to increased propagation delays and incorrect state values in synchronous digital systems.
Innovation Solution
The synthesis of a type-matched gated clock tree, where each logic gate in a level has a common logic type, either by configuring non-buffer logic gates as logic-gate buffers or transforming them into their NAND-gate equivalents, to ensure consistent propagation delays across the clock tree.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different types of logic gates are used within the same level of a clock tree, then the clock tree can accommodate diverse functional requirements and be more versatile, but clock skew increases due to different propagation delays introduced by different gate types
Solution Approach 1:
The patent applies local quality by allowing different logic gate types in different levels of the clock tree while ensuring that within each specific level, all gates are of the same type. This localized uniformity within levels maintains consistent propagation delays, while the overall tree can still incorporate diverse gate types across levels to meet functional requirements.
Solution Approach 2:
The clock tree is segmented into multiple levels, with each level containing gates of a single type. This segmentation approach isolates the propagation delay characteristics within each level, preventing skew accumulation from mixed gate types while allowing functional diversity across the entire tree structure.
2Productivity
If conventional clock distribution techniques are used with complex clock trees including different types of logic gates, then the clock tree can provide clock signals to multiple state elements, but clock skew exceeds tolerable limits causing incorrect state values
Solution Approach 1:
The invention ensures that within each level of the clock tree, all logic gates are of the same type, creating localized uniformity in propagation delay characteristics. This allows the clock tree to distribute clocks to multiple state elements while maintaining timing precision within tolerable limits.
3Ease of operation
If logic gates of different types are disposed within the same level to enable clock gating and buffering, then power savings and sharper clock edges can be achieved, but propagation delays vary causing increased clock skew
Solution Approach 1:
The patent maintains local quality uniformity within each level by using identical logic gate types, ensuring consistent propagation delays. Clock gating and buffering functions are still achieved through the structured arrangement of these uniform gates across different levels, preserving functionality while eliminating timing variations.
Solution Approach 2:
By segmenting the clock tree into levels with uniform gate types, the patent isolates propagation delay characteristics within each segment. This allows clock gating and buffering operations to perform their functions while preventing delay variations from affecting the entire clock distribution network.
Data Source
AI summary
Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.